coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#23). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor) Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 revision 001 (DOC# 634545) Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 696 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 23 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Michał Żygowski (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 22: (4 comments) Patchset: PS22: Still found some inconsistencies after trying out the patch on hardware File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/6e60e8e7_9df11a21 PS22, Line 461: PCIe vGPIO VGPIO_PCIE as the pad names indicate https://review.coreboot.org/c/coreboot/+/73934/comment/dcbbbfc1_098aaa8c PS22, Line 483: GPP_SYS_VGPIO_USB Just VGPIO_USB, GPP_SYS_ prefix should be removed https://review.coreboot.org/c/coreboot/+/73934/comment/16b8b3f7_ed84c2b1 PS22, Line 536: vGPIO_PADDING Simply VGPIO, padding was left -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 22 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Apr 2023 14:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google,intel: Use common ChromeEC code for lid shutdown
by Kyösti Mälkki (Code Review) 19 Apr '23

19 Apr '23

Kyösti Mälkki has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74514 ) Change subject: mb/google,intel: Use common ChromeEC code for lid shutdown ...................................................................... mb/google,intel: Use common ChromeEC code for lid shutdown Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pch/pmutil.c M src/southbridge/intel/common/pmbase.c 10 files changed, 66 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74514/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Gerrit-Change-Number: 74514 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: lib: Perform early initialization of FW config in ramstage
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Ivy Jian, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74530 ) Change subject: lib: Perform early initialization of FW config in ramstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I was thinking about moving is_ish_enabled into mb code, so they can do whatever needed (probably call fw_config_probe). > > Anyway IMHO if we want to put something manipulates device tree in BS_PRE_DEVICE we may need more opinions from coreboot community. for now, i will decouple this cl from the patch train as some more discussion are required -- To view, visit https://review.coreboot.org/c/coreboot/+/74530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36e7c7d2edc74a2b7fcc192690af73651e87183 Gerrit-Change-Number: 74530 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 14:05:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Paul Menzel, Sridhar Siricilla, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74435/comment/74b3f575_239c9fd6 PS1, Line 14: : This is because the current code only checks if the ME is : disabled for CSE LITE SKUs. With this patch, boot times are : approximately 5 seconds quicker: > Gotcha - but we need to use the heci method as pmc method causes issues switching between coreboot and UEFI BIOS. there are multiple ways to make CSE function disable. Please check if ur PMC.fw doesn't support CSE disablement using PMC IPC or not. > > > > this is expected behavior > > Sure, but a 5s delay isn't ideal. Any objection to this patch? Alternatively, could check the `me_state` cmos setting and skip the EOP accordingly. You patch tries to make CSE disable irrespective of whether its booting in normal or recovery mode and just check if CSE is in soft temp mode. IMO, this is valid bt would let Intel team to confirm. -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 14:01:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Sean Rhodes (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Sridhar Siricilla, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74435/comment/582aaa7c_57782168 PS1, Line 14: : This is because the current code only checks if the ME is : disabled for CSE LITE SKUs. With this patch, boot times are : approximately 5 seconds quicker: > > "the idea"? […] Gotcha - but we need to use the heci method as pmc method causes issues switching between coreboot and UEFI BIOS. > this is expected behavior Sure, but a 5s delay isn't ideal. Any objection to this patch? Alternatively, could check the `me_state` cmos setting and skip the EOP accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 13:57:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Kconfig: Set better defaults for building romstage
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Frans Hendriks, Arthur Heymans, Andrey Petrov. Hello Erik van den Bogaert, build bot (Jenkins), Sean Rhodes, Frans Hendriks, Paul Menzel, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63419 to look at the new patch set (#41). Change subject: Kconfig: Set better defaults for building romstage ...................................................................... Kconfig: Set better defaults for building romstage On x86 there is generally no reason to have a separate romstage unless VBOOT_STARTS_IN_BOOTBLOCK is used. Change-Id: I4c53b6fa7a3e66415c5b1c539918a6c1cd8defa1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/soc/intel/apollolake/Kconfig M src/vendorcode/eltan/security/mboot/Kconfig 4 files changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63419/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/63419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c53b6fa7a3e66415c5b1c539918a6c1cd8defa1 Gerrit-Change-Number: 63419 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: Allow to build romstage sources inside the bootblock
by Arthur Heymans (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Raul Rangel, Jakub Czapiga, ron minnich, Paul Menzel, Stefan Reinauer, Julius Werner, Angel Pons, Keith Hui, Patrick Rudolph, Branden Waldner, Martin L Roth, Christian Walter, Yu-Ping Wu, Felix Held. Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Philipp Hug, Jakub Czapiga, Frans Hendriks, ron minnich, Stefan Reinauer, Subrata Banik, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Piotr Król, Erik van den Bogaert, Jason Glenesk, Michał Żygowski, Martin L Roth, Marshall Dawson, Christian Walter, Yu-Ping Wu, ron minnich, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55068 to look at the new patch set (#38). Change subject: Allow to build romstage sources inside the bootblock ...................................................................... Allow to build romstage sources inside the bootblock Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/Kconfig M src/arch/arm64/romstage.c M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/arch/x86/memcpy.c M src/arch/x86/memlayout.ld M src/arch/x86/memmove_32.c M src/arch/x86/memset.c M src/commonlib/storage/sdhci.c M src/console/Kconfig M src/console/console.c M src/console/init.c M src/cpu/x86/cache/cache.c M src/drivers/net/ne2k.c M src/drivers/siemens/nc_fpga/nc_fpga_early.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/ne2k.h M src/include/console/qemu_debugcon.h M src/include/console/spkmodem.h M src/include/console/system76_ec.h M src/include/console/uart.h M src/include/console/usb.h M src/include/memlayout.h M src/include/rules.h M src/include/symbols.h M src/include/timestamp.h M src/lib/asan.c M src/lib/cbfs.c M src/lib/prog_loaders.c M src/mainboard/emulation/qemu-armv7/romstage.c M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/poppy/variants/nautilus/sku.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/ti/beaglebone/romstage.c M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/log-tpm1.c M src/security/tpm/tspi/log-tpm2.c M src/security/tpm/tspi/log.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/vboot_common.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/quark/storage_test.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M tests/lib/imd_cbmem-test.c 60 files changed, 161 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages
by Kapil Porwal (Code Review) 19 Apr '23

19 Apr '23

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74563 ) Change subject: [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages ...................................................................... [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I30db94de7f854ba444f30d9af682dd2e30f85874 --- M src/drivers/wwan/fm/acpi_fm350gl.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74563/1 diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c index e9e83c2..e6c8ee2 100644 --- a/src/drivers/wwan/fm/acpi_fm350gl.c +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -93,6 +93,7 @@ { char mutex_path[128]; + acpigen_write_debug_string("FHRF:"); if (wwan_fm350gl_rtd3_use_rp_mutex(config)) { snprintf(mutex_path, sizeof(mutex_path), acpi_device_path_join(parent_dev, RP_MUTEX_NAME)); @@ -120,6 +121,7 @@ acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_WARM); { acpigen_write_sleep(FM350GL_TBTG); + acpigen_write_debug_string(" Warm reset."); } /* cold reset */ acpigen_write_else(); @@ -137,6 +139,7 @@ /* assert FCPO# pin */ acpigen_enable_tx_gpio(&config->fcpo_gpio); acpigen_write_sleep(FM350GL_TFDI); + acpigen_write_debug_string(" Cold reset."); } acpigen_write_if_end(); /* If */ } @@ -158,6 +161,7 @@ { char mutex_path[128]; + acpigen_write_debug_string("SHRF:"); if (wwan_fm350gl_rtd3_use_rp_mutex(config)) { snprintf(mutex_path, sizeof(mutex_path), acpi_device_path_join(parent_dev, RP_MUTEX_NAME)); @@ -283,6 +287,7 @@ ARRAY_SIZE(power_res_dev_states)); acpigen_write_method_serialized("_STA", 0); + acpigen_write_debug_string("FM PR _STA:"); /* Read GPIO status into Local0. */ acpigen_get_tx_gpio(&config->perst_gpio); acpigen_write_if(); @@ -294,6 +299,7 @@ /* Method (_ON, 0, Serialized) */ acpigen_write_method_serialized("_ON", 0); + acpigen_write_debug_string("FM PR _ON:"); /* Local0 = _STA () */ acpigen_write_store(); acpigen_emit_namestring("_STA"); @@ -308,6 +314,7 @@ /* Method (_OFF, 0, Serialized) */ acpigen_write_method_serialized("_OFF", 0); + acpigen_write_debug_string("FM PR _OFF:"); /* Call FHRF i.e. Modem OFF */ acpigen_emit_namestring("FHRF"); acpigen_emit_byte(RESET_TYPE_COLD); -- To view, visit https://review.coreboot.org/c/coreboot/+/74563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30db94de7f854ba444f30d9af682dd2e30f85874 Gerrit-Change-Number: 74563 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled
by Subrata Banik (Code Review) 19 Apr '23

19 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Paul Menzel, Sridhar Siricilla, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 ) Change subject: soc/intel/common: Fix long delay when ME is disabled ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74435/comment/42c5327d_eac29903 PS1, Line 14: : This is because the current code only checks if the ME is : disabled for CSE LITE SKUs. With this patch, boot times are : approximately 5 seconds quicker: > "the idea"? I mean to say the implementation is to make CSE function disable using PMC IPC below two lines are justifying the same here. ``` [INFO ] CSE is disabled, continuing boot [INFO ] Disabling Heci using PMC IPC ``` this is expected behavior -- To view, visit https://review.coreboot.org/c/coreboot/+/74435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Gerrit-Change-Number: 74435 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Apr 2023 13:53:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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