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Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
> @Sridhar […]
BTW, I am referring to CSE Firmware version which can be read from CSE RW Blob's metadata which resides in the CBFS.
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Change subject: mb/amd/birman: Update DXIO descriptors per schematic
......................................................................
Patch Set 18:
(2 comments)
File src/mainboard/amd/birman/port_descriptors_phoenix.c:
https://review.coreboot.org/c/coreboot/+/69705/comment/6d96d6c5_9e618c4f
PS16, Line 113: .start_logical_lane = 15, \
: .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \
> can the start lane be greater than the end lane? might be a good idea to try if the dxio logic will […]
Tested and checked the logs in FSP - it detects the reversed order case and handles it properly
File src/mainboard/amd/birman/port_descriptors_phoenix.c:
https://review.coreboot.org/c/coreboot/+/69705/comment/045406ef_6fdee468
PS17, Line 65: CLK_REQ4
> CLK_REQ1?
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/amd/birman: Update DXIO descriptors per schematic
......................................................................
mb/amd/birman: Update DXIO descriptors per schematic
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B
v0.7
Update devicetree to reference the updated DXIO descriptors.
TEST=boot birman and note the devices show up in the logs correctly
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
---
M src/mainboard/amd/birman/devicetree_phoenix.cb
M src/mainboard/amd/birman/port_descriptors_phoenix.c
2 files changed, 196 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69705/18
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Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS19:
@Sridhar
> Otherway this can be done by just checking the CSE Lite version in the CSE RW blob's metadata. In this scenario, coreboot need not interact with CSE and checking CSE blob only once is required. We plan to add the change later one this patchtrain get merged.
Again, it is intentional to talk to CSE and get the ISH version. Parsing BPDT and sub-partition headers is not 100% correct - e.g. if signature verification is failed CSE will silently fail and not load ISH firmware without any indication.
So we think getting the running ISH firmware version directly from CSE is necessary to ensure that SoC is running the ISH firmware we intended.
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Change subject: lib: Perform early initialization of FW config in ramstage
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > Maybe add stage check like this CL? https://review.coreboot.org/c/coreboot/+/54752 […]
I was thinking about moving is_ish_enabled into mb code, so they can do whatever needed (probably call fw_config_probe).
Anyway IMHO if we want to put something manipulates device tree in BS_PRE_DEVICE we may need more opinions from coreboot community.
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Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
Patch Set 22:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73934/comment/2de0e9e1_34d733d9
PS21, Line 9: Tested on: GW-R86S-P1
> This name is not descriptive, we typically add TEST= at the end of commit message with explanation h […]
Done
https://review.coreboot.org/c/coreboot/+/73934/comment/c8cbd1bf_5b04e021
PS21, Line 10: Documents: Intel Datasheet: 634545, rev. 001
: Document Number: Intel Pentium Silver and Intel
: Celeron Processor Datasheet, vol. 2 of 2
> Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. […]
Done
Patchset:
PS22:
Corrected, regarding your comment.
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Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
util/inteltool: Add support for Jasper Lake
Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor)
Based on Intel Pentium Silver and Intel Celeron Processor Datasheet,
vol. 2 of 2 revision 001 (DOC# 634545)
Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
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---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/jasperlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 696 insertions(+), 0 deletions(-)
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Change subject: Kconfig: Set better defaults for building romstage
......................................................................
Patch Set 40:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63419/comment/dd3efd35_de3165ed
PS36, Line 11:
> Could you please explain/mention the ARCH_X86_64_PGTBL_LOC changes?
Factored out into https://review.coreboot.org/c/coreboot/+/74560/.
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Change subject: arch/x86/Kconfig: Change default pt location if !SEPARATE_ROMSTAGE
......................................................................
arch/x86/Kconfig: Change default pt location if !SEPARATE_ROMSTAGE
When romstage code is linked inside the bootblock it gets bigger so move
the page tables up.
Change-Id: Iea13d53c13c2744c1ab5bb48f872614652b5fccd
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74560/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 8d2295b..e09f44a 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -87,6 +87,7 @@
config ARCH_X86_64_PGTBL_LOC
hex "x86_64 page table location in CBFS"
depends on ARCH_BOOTBLOCK_X86_64
+ default 0xfffe3000 if !SEPARATE_ROMSTAGE
default 0xfffe9000
help
The position where to place pagetables. Needs to be known at
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Hello Erik van den Bogaert, build bot (Jenkins), Sean Rhodes, Frans Hendriks, Paul Menzel, Andrey Petrov,
I'd like you to reexamine a change. Please visit
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Change subject: Kconfig: Set better defaults for building romstage
......................................................................
Kconfig: Set better defaults for building romstage
On x86 there is generally no reason to have a separate romstage unless
VBOOT_STARTS_IN_BOOTBLOCK is used.
Change-Id: I4c53b6fa7a3e66415c5b1c539918a6c1cd8defa1
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---
M src/Kconfig
M src/mainboard/facebook/fbg1701/Kconfig
M src/soc/intel/apollolake/Kconfig
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