Arthur Heymans has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/74548 )
Change subject: vendorcode/mediatek/mt8195: Fix set but unused variables
......................................................................
vendorcode/mediatek/mt8195: Fix set but unused variables
The clang compiler warns about this.
Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/vendorcode/mediatek/mt8195/dramc/Hal_io.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
M src/vendorcode/mediatek/mt8195/dramc/emi.c
M src/vendorcode/mediatek/mt8195/include/dramc_common.h
M src/vendorcode/mediatek/mt8195/include/x_hal_io.h
8 files changed, 36 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74548/5
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Gerrit-Change-Number: 74548
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Hello Xi Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables
......................................................................
vendorcode/mediatek/mt8192: Fix set but unused variables
TEST: BUILD_TIMELESS=1 binary remains the same.
Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
M src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
M src/vendorcode/mediatek/mt8192/dramc/emi.c
M src/vendorcode/mediatek/mt8192/include/dramc_common.h
M src/vendorcode/mediatek/mt8192/include/x_hal_io.h
6 files changed, 19 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74543/3
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 )
Change subject: soc/intel/common: Fix long delay when ME is disabled
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74435/comment/5e40b1e3_23038af5
PS1, Line 14:
: This is because the current code only checks if the ME is
: disabled for CSE LITE SKUs. With this patch, boot times are
: approximately 5 seconds quicker:
> So `cse_is_hfs1_com_soft_temp_disable()` took that long, and is skipped now with your patch from `&& […]
"
[ERROR] HECI: Prerequisites not met for sending EOP
[ERROR] HECI: timed out reading answer!
[ERROR] HECI: Failed to receive!
[DEBUG] HECI: Trigger HECI Reset
[ERROR] HECI: Prerequisites not met for sending EOP
[INFO ] CSE is disabled, continuing boot
[INFO ] Disabling Heci using PMC IPC
"
Debug message flow is confusing.. which HECI command has been sent to CSE? Of cousre, it can't be EOP as prerequisites are not met as per the debug messages.
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Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/amd/common/block/gfx: Re-add signature check for vbios cache
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/74525/comment/cc8c41bf_07195793
PS1, Line 266:
> nit: space
Done
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Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/amd/common/block/gfx: Re-add signature check for vbios cache
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/74525/comment/a87dfdb6_f28b8dad
PS1, Line 266:
nit: space
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/common/block/gfx: Re-add signature check for vbios cache
......................................................................
soc/amd/common/block/gfx: Re-add signature check for vbios cache
Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash
for vbios cache validation") replaced checking the vbios signature
(first two bytes) with checking against a TPM-stored hash, but there
exists an edge case where the empty cache can be hashed and therefore
never updated with the correct vbios data. To mitigate this, re-add
the signature check to ensure that an empty cache will never be hashed
to TPM.
BUG=b:255812886
BRANCH=skyrim
TEST=build/boot skyrim w/selective GOP enabled, flash full firmware
image, ensure GOP driver is run until cache updated with valid data
and hashed to TPM.
Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/graphics/graphics.c
1 file changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/74525/2
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Change subject: soc/amd/common/block/gfx: Re-add signature check for vbios cache
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174506):
https://review.coreboot.org/c/coreboot/+/74525/comment/d9f223d2_7b37ac7a
PS1, Line 21: TEST=build/boot skyrim w/selective GOP enabled, flash full firmware image,
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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