coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb
by Jason Glenesk (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74615 ) Change subject: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Gerrit-Change-Number: 74615 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 15:10:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Raul Rangel, Felix Held, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74110 ) Change subject: mb/google/myst: Add eSPI configuration ...................................................................... Patch Set 33: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74110/comment/03456531_2faea4b3 PS33, Line 22: 255 > hmm, this should probably be 256. […] It appears to be correlated to EC_MEMMAP_SIZE and the buffer used on the other side is driven by that macro, can we file a follow up bug to investigate? https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/pla… -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 14:56:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 20 Apr '23

20 Apr '23

Sumeet R Pawnikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74621 ) Change subject: mb/google/rex: Add CPU power limit values ...................................................................... Abandoned Pushed this new patch by mistake, instead of updating previous one. -- To view, visit https://review.coreboot.org/c/coreboot/+/74621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia20421f73758b7b0266fba957fb8200439ce1dab Gerrit-Change-Number: 74621 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/phoenix: Add note clarifying the eMMC controller
by Martin L Roth (Code Review) 20 Apr '23

20 Apr '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74590 ) Change subject: soc/amd/phoenix: Add note clarifying the eMMC controller ...................................................................... Abandoned Maybe this is a PPR bug? The registers on the silicon come back as 0xff. Filing a bug against the PPR. -- To view, visit https://review.coreboot.org/c/coreboot/+/74590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ffd9792cbdc174d9eab7aa14d1bd6b89e1c817 Gerrit-Change-Number: 74590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: Revert "soc/amd/morgana: Remove emmc select"
by Martin L Roth (Code Review) 20 Apr '23

20 Apr '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74529 ) Change subject: Revert "soc/amd/morgana: Remove emmc select" ...................................................................... Abandoned Maybe this is a PPR bug? The registers on the silicon come back as 0xff. Filing a bug against the PPR. -- To view, visit https://review.coreboot.org/c/coreboot/+/74529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84f16f27886ca866e5ac3c5a06ee1e32df617d32 Gerrit-Change-Number: 74529 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/rex: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74379 to look at the new patch set (#2). Change subject: mb/google/rex: Add CPU power limit values ...................................................................... mb/google/rex: Add CPU power limit values Add CPU power limit values for Meteor Lake based rex board BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/rex0/Makefile.inc A src/mainboard/google/rex/variants/rex0/ramstage.c 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/74379/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Gerrit-Change-Number: 74379 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex/baseboard/rex: Add cpu power limits
by Sumeet R Pawnikar (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74379 ) Change subject: mb/google/rex/baseboard/rex: Add cpu power limits ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/rex/variants/baseboard/rex/ramstage.c: https://review.coreboot.org/c/coreboot/+/74379/comment/1953c7d7_fd7d1675 PS1, Line 15: void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) > this section can be part of power_limit.c. this is the same code like ADL one... Ack. Created patch https://review.coreboot.org/c/coreboot/+/74620 moving this section to power_limit.c File src/mainboard/google/rex/variants/rex0/ramstage.c: https://review.coreboot.org/c/coreboot/+/74379/comment/23e8a802_85dc85d9 PS1, Line 17: variant_update_power_limits > we can call this directly from systemagent.c. no need hook up from variant_devtree_update. […] I feel we need this here for variants to set during ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/74379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7953ce8dc0a247d440154902cef1007eb9358dc1 Gerrit-Change-Number: 74379 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 14:46:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vga: Change the arguments of vga_write_text to support extended ASCII
by Tarun Tuli (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Hsuan-ting Chen. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73099 ) Change subject: vga: Change the arguments of vga_write_text to support extended ASCII ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Gerrit-Change-Number: 73099 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 14:41:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74621 ) Change subject: mb/google/rex: Add CPU power limit values ...................................................................... mb/google/rex: Add CPU power limit values Add CPU power limit values to override for rex board BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: Ia20421f73758b7b0266fba957fb8200439ce1dab Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/rex0/Makefile.inc A src/mainboard/google/rex/variants/rex0/ramstage.c 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74621/1 diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index c1c22db..7d5f01d 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -30,6 +30,12 @@ fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ } void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index b51517c..3cb1fb2 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -29,4 +29,7 @@ void variant_generate_s0ix_hook(enum s0ix_entry entry); +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/rex/variants/rex0/Makefile.inc b/src/mainboard/google/rex/variants/rex0/Makefile.inc index cdbf407..95a700a 100644 --- a/src/mainboard/google/rex/variants/rex0/Makefile.inc +++ b/src/mainboard/google/rex/variants/rex0/Makefile.inc @@ -2,4 +2,5 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/rex/variants/rex0/ramstage.c b/src/mainboard/google/rex/variants/rex0/ramstage.c new file mode 100644 index 0000000..c2d32af --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/ramstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* Following values are for performance config as per document #640982 */ + { PCI_DID_INTEL_MTL_P_ID_2, 15, 6000, 15000, 57000, 57000, 101000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia20421f73758b7b0266fba957fb8200439ce1dab Gerrit-Change-Number: 74621 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common: add power limits update support for variants
by Sumeet R Pawnikar (Code Review) 20 Apr '23

20 Apr '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74620 ) Change subject: soc/intel/common: add power limits update support for variants ...................................................................... soc/intel/common: add power limits update support for variants Add support to update power limit values for variants. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/74620/1 diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 3f18126..140c209 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -42,4 +42,17 @@ u8 get_cpu_tdp(void); +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(const struct cpu_power_limits *limits, + size_t num_entries); + #endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */ diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index d7c9077..935514d 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -2,11 +2,16 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <device/pci_ops.h> #include <intelblocks/cpulib.h> #include <intelblocks/power_limit.h> #include <soc/msr.h> +#include <soc/soc_chip.h> +#include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <drivers/intel/dptf/chip.h> + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -227,3 +232,40 @@ return cpu_tdp / power_unit; } + +WEAK_DEV_PTR(dptf_policy); + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4(W) (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb Gerrit-Change-Number: 74620 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2023