coreboot-gerrit April 2023

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[S] Change in coreboot[master]: [RFC] include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74619 ) Change subject: [RFC] include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: i'm not entirely sure if this makes things more or less confusing -- To view, visit https://review.coreboot.org/c/coreboot/+/74619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 Gerrit-Change-Number: 74619 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 14:13:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74619 ) Change subject: [RFC] include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround ...................................................................... [RFC] include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since it was defined as unsigned long in AGESA.h, a workaround was needed in cpu/amd/mtrr.h to not have the build fail due to a non-identical redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround without reaming the defines isn't trivially possible, since the stoneyridge romstage.c still ends up including both definitions which can't be easily worked around. Now all non-vendorcode coreboot code uses TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and TOP_MEM2 to avoid this. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 --- M src/drivers/amd/agesa/s3_mtrr.c M src/include/cpu/amd/mtrr.h 2 files changed, 26 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/74619/1 diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 51e8a4d..55c9c40 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -39,8 +39,8 @@ MTRR_PHYS_BASE(7), MTRR_PHYS_MASK(7), SYSCFG_MSR, - TOP_MEM, - TOP_MEM2, + TOP_MEM_MSR, + TOP_MEM2_MSR, }; void backup_mtrr(void) diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index e96dc90..57edfe6 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -29,13 +29,8 @@ #define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) #define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) -#if defined(__ASSEMBLER__) -#define TOP_MEM 0xC001001A -#define TOP_MEM2 0xC001001D -#else -#define TOP_MEM 0xC001001Aul -#define TOP_MEM2 0xC001001Dul -#endif +#define TOP_MEM_MSR 0xC001001A +#define TOP_MEM2_MSR 0xC001001D #if !defined(__ASSEMBLER__) @@ -67,12 +62,12 @@ static inline uint32_t get_top_of_mem_below_4gb(void) { - return rdmsr(TOP_MEM).lo; + return rdmsr(TOP_MEM_MSR).lo; } static inline uint64_t get_top_of_mem_above_4g(void) { - msr_t msr = rdmsr(TOP_MEM2); + msr_t msr = rdmsr(TOP_MEM2_MSR); return (uint64_t)msr.hi << 32 | msr.lo; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 Gerrit-Change-Number: 74619 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74618 ) Change subject: nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include ...................................................................... nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include TEST=Timeless build for pcengines/apu2 results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If95eb9e5135de2b256d1f584afcedfd6e0cf8d8e --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/74618/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d373493..cba57d8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,7 +15,6 @@ #include <lib.h> #include <cpu/x86/mp.h> #include <Porting.h> -#include <AGESA.h> #include <Topology.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/74618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95eb9e5135de2b256d1f584afcedfd6e0cf8d8e Gerrit-Change-Number: 74618 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: replace some magic numbers
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74617 ) Change subject: cpu/amd/pi/00730F01/fixme: replace some magic numbers ...................................................................... cpu/amd/pi/00730F01/fixme: replace some magic numbers TEST=Timeless build for pcengines/apu2 results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec --- M src/cpu/amd/pi/00730F01/fixme.c 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/74617/1 diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index d36f507..9724133 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -3,6 +3,7 @@ #include <amdblocks/pci_devs.h> #include <arch/hpet.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -16,13 +17,14 @@ * set to non-posted regions. Last address before processor local APIC * at FEE00000, set NP (non-posted) bit. */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7)); + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, + ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7)); /* lowest NP address is HPET at FED00000 */ pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last - address before non-posted range */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00); + /* Map the remaining PCI hole as posted MMIO. */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, + ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); /* Send all IO (0000-FFFF) to southbridge. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec Gerrit-Change-Number: 74617 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions Use coreboot's native PCI access functions instead of using the vendorcode's PCI access functions to set up the CPU IO routing in function 1 of the HT PCI device. This file still has room for improvement, but at least it's now using coreboot-native functionality. Stoneyridge has a nicer implementation, but looking into possibly unifying those is out of scope for this patch. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c --- M src/cpu/amd/pi/00730F01/fixme.c 1 file changed, 32 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/74616/1 diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index bc649b7..d36f507 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,54 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/pci_devs.h> #include <arch/hpet.h> #include <cpu/amd/mtrr.h> +#include <device/pci.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> void amd_initcpuio(void) { - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. + * set to non-posted regions. Last address before processor local APIC + * at FEE00000, set NP (non-posted) bit. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; - /* set NP (non-posted) bit */ - PciData |= 1 << 7; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7)); /* lowest NP address is HPET at FED00000 */ - PciData = (HPET_BASE_ADDRESS >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last + address before non-posted range */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00); + pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000); + pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74615 ) Change subject: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb ...................................................................... soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 --- M src/soc/amd/common/block/cpu/noncar/early_cache.c 1 file changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/74615/1 diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index 4bba172..2ff8760 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -20,7 +20,6 @@ */ void early_cache_setup(void) { - msr_t top_mem; msr_t sys_cfg; msr_t mtrr_def_type; msr_t fixed_mtrr_ram; @@ -34,7 +33,6 @@ var_mtrr_context_init(&mtrr_ctx.ctx); mtrr_ctx.ctx.max_var_mtrrs = MIN(MAX_VAR_MTRR_USE, mtrr_ctx.ctx.max_var_mtrrs); - top_mem = rdmsr(TOP_MEM); /* Enable RdDram and WrDram attributes in fixed MTRRs. */ sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -61,7 +59,8 @@ wrmsr(SYSCFG_MSR, sys_cfg); - var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8 * MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(get_top_of_mem_below_4gb(), 8 * MiB), + MTRR_TYPE_WRBACK); /* Always mark the 16 MByte right below the 4 GB boundary as WRPROT */ var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); -- To view, visit https://review.coreboot.org/c/coreboot/+/74615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Gerrit-Change-Number: 74615 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74614 ) Change subject: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb ...................................................................... soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 --- M src/soc/amd/stoneyridge/memmap.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74614/1 diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 8f73a8c..32d6d96 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,9 +13,7 @@ uintptr_t cbmem_top_chipset(void) { - msr_t tom = rdmsr(TOP_MEM); - - if (!tom.lo) + if (!get_top_of_mem_below_4gb()) return 0; /* 8MB alignment to keep MTRR usage low */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Gerrit-Change-Number: 74614 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74613 ) Change subject: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb ...................................................................... soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74613/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7ddfc41..23395d3 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -327,8 +327,8 @@ uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); uint32_t mem_useable = (uintptr_t)cbmem_top(); - msr_t tom = rdmsr(TOP_MEM); - msr_t high_tom = rdmsr(TOP_MEM2); + uint32_t tom = get_top_of_mem_below_4gb(); + uint64_t high_tom = get_top_of_mem_above_4g(); uint64_t high_mem_useable; int idx = 0x10; @@ -352,16 +352,15 @@ /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource_kb(dev, idx++, mem_useable / KiB, - (tom.lo - mem_useable) / KiB); + (tom - mem_useable) / KiB); /* If there is memory above 4GiB */ - if (high_tom.hi) { + if (high_tom >> 32) { /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else - high_mem_useable = ((uint64_t)high_tom.lo | - ((uint64_t)high_tom.hi << 32)); + high_mem_useable = high_tom; ram_resource_kb(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); -- To view, visit https://review.coreboot.org/c/coreboot/+/74613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Gerrit-Change-Number: 74613 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74612 ) Change subject: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb ...................................................................... soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 --- M src/soc/amd/common/block/acpi/tables.c 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74612/1 diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index b7c942c..17db421 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -40,7 +40,6 @@ /* Used by \_SB.PCI0._CRS */ void acpi_fill_root_complex_tom(const struct device *device) { - msr_t msr; const char *scope; assert(device); @@ -49,9 +48,8 @@ assert(scope); acpigen_write_scope(scope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + /* * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. @@ -60,6 +58,6 @@ * Shift value right by 20 bit to make it fit into 32bit, * giving us 1MB granularity and a limit of almost 4Exabyte of memory. */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4g() >> 20); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Gerrit-Change-Number: 74612 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74611 ) Change subject: nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb ...................................................................... nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/74611/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d963171..d373493 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -538,13 +538,11 @@ static void northbridge_fill_ssdt_generator(const struct device *device) { - msr_t msr; char pscope[] = "\\_SB.PCI0"; acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + /* * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. @@ -553,7 +551,7 @@ * Shift value right by 20 bit to make it fit into 32bit, * giving us 1MB granularity and a limit of almost 4Exabyte of memory. */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4g() >> 20); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd Gerrit-Change-Number: 74611 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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