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Change subject: mb/google/rex: Add CPU power limit values
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
Please split this CL into 2 Cls
1. mainboard.c and variant.h
2. Makefile.inc and ramstage.c
File src/mainboard/google/rex/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74379/comment/143956ee_271edd7a
PS2, Line 36: variant_devtree_update
why we need to do this override for per variant rather than baseboard ?
for example: both rex and screebo will use same 281 SoC hence, the MTL MCH ID will be same.
what would benefit to repeat this going forward for all 30+ variants in scope of rex baseboard using all same SoC SPEC#
I would have allow to have baseboard specific override for example:rex being the baseboard for all chromebooks with MTL SoC can leverage this. Also allow Ovis baseboard(for chromebox) with MTL SoC (may be 28W) can use the baseboard specific override.
File src/mainboard/google/rex/variants/rex0/ramstage.c:
https://review.coreboot.org/c/coreboot/+/74379/comment/c6db7ee1_e26b915e
PS2, Line 17: }
I prefer to make it visible to know what we are filling into.
```
void variant_devtree_update(void)
{
struct cpu_power_limits limits[] = {
{
.mchid = 123,
.cpu_tdp = 15,
.pl1_min_power = 6000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
.pl2_max_power = 57000,
.pl4_power = 101000,
},
};
size_t total_entries = ARRAY_SIZE(limits);
variant_update_power_limits(limits, total_entries);
}
```
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74289 )
Change subject: crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> although i don't expect this to cause any trouble, i'd strongly prefer if the tooling was upgraded a […]
I agree.
but CMake is only used by Clang which is experimental.
As long as Clang is not "supported - meaning experimental", I think that this upgrade is harmless.
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Change subject: util/crossgcc/buildgcc: Drop some superfluous comments
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I think , this is to distinguish what is supported and what is experimental.
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Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74622 )
Change subject: mb/google/octopus: Add EC_HOST_EVENT_PANIC to SCI mask
......................................................................
mb/google/octopus: Add EC_HOST_EVENT_PANIC to SCI mask
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:268342532
BRANCH=firmware-octopus-11297.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6
---
M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/74622/1
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
index 914da13..857c1f9 100644
--- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
@@ -19,7 +19,8 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
......................................................................
Patch Set 3: Code-Review+2
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Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Patch Set 7:
(1 comment)
File Documentation/mainboard/hp/compaq_8200_sff.md:
https://review.coreboot.org/c/coreboot/+/74248/comment/6e3a9885_e61bc84e
PS5, Line 87: The final flash layout after you already have the temporary coreboot
: installation running should look like this:
> What adding adding "Keep in mind this layout is intended to be used with the truncated ME. […]
Done
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Hello build bot (Jenkins), Nicholas Chin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74248
to look at the new patch set (#7).
Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Documentation/mainboard/hp: Add more about internal flashing
Add a more detailed explanation of internal flashing
on the HP Compaq 8200 Elite SFF.
Signed-off-by: Václav Straka <venda.straka(a)gmail.com>
Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636
---
M Documentation/mainboard/hp/compaq_8200_sff.md
A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg
2 files changed, 94 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/7
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Change subject: soc/amd/common: Update GPIO macros
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> on some of the older socs the internal gpio number doesn't match the gpio number on the package depe […]
The only solution I can think of at the moment is to create a duplicate of each of the macros that accepts a value and uses the method in the first patchset to build the string. Users can select whichever is needed for their project. Existing projects would then be unaffected.
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 33:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74110/comment/b0337137_1e55051e
PS33, Line 22: 255
> sure. […]
b/279026734
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 33:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74110/comment/7c45305a_f61332d9
PS33, Line 22: 255
> It appears to be correlated to EC_MEMMAP_SIZE and the buffer used on the other side is driven by tha […]
sure. would be good if you can create a bug to track this though
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