Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74610 )
Change subject: include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb
......................................................................
include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb
The top of memory below 4GB will always fit into 32 bits, so change the
return type accordingly.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431
---
M src/include/cpu/amd/mtrr.h
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74610/1
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index b8b820c..e96dc90 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -65,7 +65,7 @@
);
}
-static inline uint64_t get_top_of_mem_below_4gb(void)
+static inline uint32_t get_top_of_mem_below_4gb(void)
{
return rdmsr(TOP_MEM).lo;
}
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Change subject: soc/amd/phoenix: Add note clarifying the eMMC controller
......................................................................
Patch Set 1: -Code-Review
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74529 )
Change subject: Revert "soc/amd/morgana: Remove emmc select"
......................................................................
Patch Set 1: -Code-Review
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
......................................................................
mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:278495684
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e
---
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74583/3
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Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
......................................................................
mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMc clkreq signal instead.
BRANCH=none
BUG=b:278495684
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e
---
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
1 file changed, 23 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74583/2
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Change subject: soc/amd/phoenix: Add note clarifying the eMMC controller
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I think the PPR might be wrong in this case - unable to read the MMIO registers
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Change subject: Revert "soc/amd/morgana: Remove emmc select"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Trying to test this, I don't think the eMMC is actually in the SoC
Attempts to read the MMIO register are not showing expected values
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Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables
......................................................................
Patch Set 5: -Code-Review
(1 comment)
File src/vendorcode/mediatek/mt8192/include/dramc_common.h:
https://review.coreboot.org/c/coreboot/+/74543/comment/3f81d691_3a551b65
PS5, Line 58: #define msg2(_x_...) { if (0) { print(_x_); } } // { print(_x_); }
> The comment can be removed now?
Agree, the comment can be removed.
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Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74544/comment/c892396f_60cfefe5
PS5, Line 9: BUILD_TIMELESS
> … and no commit hash (which can also be considered a (transformed/indirect) timestamp).
Got it.
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