coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Generate SPD ID for supported memory part
by Kevin3 Yang (Code Review) 20 Apr '23

20 Apr '23

Kevin3 Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74586 ) Change subject: mb/google/dedede/var/boxy: Generate SPD ID for supported memory part ...................................................................... mb/google/dedede/var/boxy: Generate SPD ID for supported memory part Add boxy supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 3. Micron MT53E512M32D1NP-046 WT:B BUG=b:278983561 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang(a)lcfc.corp-partner.google.com> Change-Id: I317f2b31774627706babdea10776af05ab692d1e --- M src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc M src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt 3 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/74586/1 diff --git a/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc index eace2e4..fa024d4 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/boxy/memory/ src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt index fa24790..52ffb42 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/boxy/memory/ src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt index 9621137..f971a01 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt @@ -9,3 +9,6 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/74586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317f2b31774627706babdea10776af05ab692d1e Gerrit-Change-Number: 74586 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages
by Kapil Porwal (Code Review) 20 Apr '23

20 Apr '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74563 to look at the new patch set (#2). Change subject: [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages ...................................................................... [TEST][Do Not Merge] drivers/wwan/fm: Add debug messages To see ACPI debug messages in dmesg output, execute - echo 1 > /sys/module/acpi/parameters/aml_debug_output Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I30db94de7f854ba444f30d9af682dd2e30f85874 --- M src/drivers/wwan/fm/acpi_fm350gl.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74563/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30db94de7f854ba444f30d9af682dd2e30f85874 Gerrit-Change-Number: 74563 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74110 ) Change subject: mb/google/myst: Add eSPI configuration ...................................................................... Patch Set 33: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74110/comment/6120bec6_e2520c97 PS33, Line 22: 255 hmm, this should probably be 256. it's also 255 on all other amd zen based chromebooks, but this is likely missing the last byte on all. the io region above uses the expected 256 bytes which also points at the 255 being wrong. espi_write_io_window already subtracts the 1 from the size struct element to get the correct register value -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 33 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 09:12:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common: Update GPIO macros
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Jon Murphy, Martin Roth, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74591 ) Change subject: soc/amd/common: Update GPIO macros ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Made an assumption that the value of the GPIO would match the macro name. […] on some of the older socs the internal gpio number doesn't match the gpio number on the package depending on the silicon and package combination. probably related to how things are bonded out on the package -- To view, visit https://review.coreboot.org/c/coreboot/+/74591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918d659eecf2076ed9089218177874ed2c9023b3 Gerrit-Change-Number: 74591 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 09:02:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74168 ) Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS The Intel FSP used on ChromeOS platform has dropped the `CpuFeaturesPei.ffs` module to opt for coreboot running this additional feature programming on BSP and APs. TEST=Able to build and boot google/rex without any boot regression. Please refer to the boot time and SPI flash savings after dropping the FSP feature programming: Boot time savings=10ms SPI Flash size savings=34KB Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Reviewed-on: https://review.coreboot.org/c/coreboot/+/74168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 3d99f81..c34f255 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -366,7 +366,7 @@ config DROP_CPU_FEATURE_PROGRAM_IN_FSP bool - default y if MP_SERVICES_PPI_V2_NOOP + default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS default n help This is to avoid FSP running basic CPU feature programming on BSP -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Refactor ramstage cse fw sync() function
by build bot (Jenkins) (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Tarun Tuli, Kangheui Won, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74581 ) Change subject: soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() function ...................................................................... Patch Set 2: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174634): https://review.coreboot.org/c/coreboot/+/74581/comment/9e8efe25_b7cdc68a PS2, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/74581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Gerrit-Change-Number: 74581 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 08:21:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has uploaded a new patch set (#25) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74208 ) Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM ...................................................................... soc/intel/cmn/cse: Store ISH firmware version into CBMEM The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 72 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 25 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has uploaded a new patch set (#21) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 128 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 21 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks
by Kevin Chiu (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Chen-Tsung Hsieh, Tony Huang, Derek Huang, Robert Chen, Shon Wang, Shou-Chieh Hsu. Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74584 ) Change subject: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Gerrit-Change-Number: 74584 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 07:58:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Michał Żygowski (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 23 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Apr 2023 07:35:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023