coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/skyrim: Update GPIO names
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74595 ) Change subject: mb/google/skyrim: Update GPIO names ...................................................................... mb/google/skyrim: Update GPIO names Update GPIO names in devicetree files to use the more descriptive versions in variant/gpio.h. This provides more clarity and insight into what GPIOs actually mean on the design. BUG=b:278968729 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I7443d1d1e3a2c00f2d2f76431f230a86faf551c6 --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb M src/mainboard/google/skyrim/variants/markarth/overridetree.cb M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 6 files changed, 70 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74595/1 diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index f863197..29c92f6 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -174,7 +174,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "has_power_resource" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_10)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(BT_DISABLE)" register "enable_delay_ms" = "500" register "enable_off_delay_ms" = "200" register "use_gpio_for_status" = "true" @@ -193,7 +193,7 @@ chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "desc" = ""Ti50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_18)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GSC_SOC_INT_L)" device i2c 50 alias ti50 on end end end diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb index 23d7f40..e746405d 100644 --- a/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb @@ -91,8 +91,8 @@ chip drivers/i2c/hid register "generic.hid" = ""PIXA2635"" register "generic.desc" = ""PIXA Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" - #register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_TCHPAD_INT_ODL)" + #register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(SOC_TCHPAD_INT_ODL)" register "generic.wake" = "GEVENT_20" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x01" @@ -105,7 +105,7 @@ register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(HP_INT_ODL)" register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index c10e0dd..19861dd 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -62,7 +62,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(SOC_TCHPAD_INT_ODL)" register "wake" = "GEVENT_20" register "detect" = "1" device i2c 15 on end @@ -72,14 +72,14 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(TCHSCR_INT_ODL)" register "generic.detect" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "generic.enable_delay_ms" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "generic.reset_off_delay_ms" = "2" register "generic.reset_delay_ms" = "20" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "generic.stop_delay_ms" = "150" register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" @@ -88,7 +88,7 @@ end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_3)" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(SOC_PEN_DETECT_ODL)" register "key.dev_name" = ""EJCT"" register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.linux_code" = "SW_PEN_INSERTED" @@ -106,7 +106,7 @@ register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(HP_INT_ODL)" register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" @@ -134,12 +134,12 @@ register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_FP_INT_L)" register "wake" = "GEVENT_15" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(SOC_FP_RST_L)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PWR_FP)" register "enable_delay_ms" = "3" device generic 0 alias fpmcu on probe FP FP_PRESENT diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb index 3939d65..46a7a45 100644 --- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb @@ -68,7 +68,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(SOC_TCHPAD_INT_ODL)" register "wake" = "GEVENT_20" register "detect" = "1" device i2c 15 on end @@ -77,7 +77,7 @@ register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_TCHPAD_INT_ODL)" register "generic.wake" = "GEVENT_20" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" @@ -88,14 +88,14 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(TCHSCR_INT_ODL)" register "generic.detect" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "generic.enable_delay_ms" = "10" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "generic.reset_off_delay_ms" = "1" register "generic.reset_delay_ms" = "10" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "generic.stop_delay_ms" = "150" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" @@ -108,7 +108,7 @@ register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(HP_INT_ODL)" register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index eb16120..0f66fe2 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -63,9 +63,9 @@ register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(2, 2)" register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_42)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(WWAN_RST)" register "reset_off_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_8)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PWR_WWAN_X)" register "enable_delay_ms" = "20" device usb 3.1 on end end @@ -121,7 +121,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(SOC_TCHPAD_INT_ODL)" register "wake" = "GEVENT_20" register "detect" = "1" device i2c 15 on end @@ -131,14 +131,14 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(TCHSCR_INT_ODL)" register "generic.detect" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "generic.enable_delay_ms" = "10" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "generic.reset_off_delay_ms" = "1" register "generic.reset_delay_ms" = "10" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "generic.stop_delay_ms" = "180" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" @@ -149,13 +149,13 @@ register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(TCHSCR_INT_ODL)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "enable_delay_ms" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "reset_delay_ms" = "20" register "reset_off_delay_ms" = "2" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "stop_off_delay_ms" = "2" register "has_power_resource" = "1" device i2c 10 on end @@ -166,7 +166,7 @@ register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(HP_INT_ODL)" register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" @@ -176,7 +176,7 @@ end end chip drivers/i2c/nau8825 - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(HP_INT_ODL)" register "jkdet_enable" = "1" register "jkdet_pull_enable" = "0" register "jkdet_polarity" = "1" # ActiveLow @@ -218,7 +218,7 @@ end # I2C2 chip drivers/generic/max98357a register "hid" = ""MX98360A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_139)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_SPKR)" register "sdmode_delay" = "5" device generic 0.1 on probe AUDIO_DB AUDIO_DB_C_NAU88L25YGB_A_MAX98360AENL @@ -231,12 +231,12 @@ register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_FP_INT_L)" register "wake" = "GEVENT_15" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(SOC_FP_RST_L)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PWR_FP)" register "enable_delay_ms" = "3" device generic 0 alias fpmcu on probe FP FP_PRESENT diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f90..f541f62 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -166,7 +166,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(SOC_TCHPAD_INT_ODL)" register "wake" = "GEVENT_20" register "detect" = "1" device i2c 15 on end @@ -174,7 +174,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GXTP7863"" register "generic.desc" = ""Goodix Touchpad"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_TCHPAD_INT_ODL)" register "generic.wake" = "GEVENT_20" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" @@ -185,14 +185,14 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(TCHSCR_INT_ODL)" register "generic.detect" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "generic.enable_delay_ms" = "10" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "generic.reset_off_delay_ms" = "1" register "generic.reset_delay_ms" = "10" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "generic.stop_delay_ms" = "150" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" @@ -203,13 +203,13 @@ register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" register "detect" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(TCHSCR_INT_ODL)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PP3300_TCHSCR)" register "enable_delay_ms" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_RST_L)" register "reset_delay_ms" = "20" register "reset_off_delay_ms" = "2" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(TCHSCR_REPORT_EN)" register "stop_off_delay_ms" = "2" register "has_power_resource" = "1" device i2c 34 on end @@ -220,7 +220,7 @@ register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(HP_INT_ODL)" register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" @@ -248,12 +248,12 @@ register "desc" = ""Fingerprint Reader"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_24)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(SOC_FP_INT_L)" register "wake" = "GEVENT_15" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_12)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(SOC_FP_RST_L)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(EN_PWR_FP)" register "enable_delay_ms" = "3" device generic 0 alias fpmcu on probe FP FP_PRESENT -- To view, visit https://review.coreboot.org/c/coreboot/+/74595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7443d1d1e3a2c00f2d2f76431f230a86faf551c6 Gerrit-Change-Number: 74595 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/sconfig/main: Add variant/gpio.h to static.c
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Martin L Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74594 ) Change subject: util/sconfig/main: Add variant/gpio.h to static.c ...................................................................... util/sconfig/main: Add variant/gpio.h to static.c Add variant/gpio.h to static.c to allow redefined GPIO names to be used within devicetree files. This will allow programs to use a more meaningful name for their GPIOs than simply GPIO_X. BUG=b:278969100, b:278968729 TEST=builds Change-Id: Ia16211ef73fa9c6221f98c36879dd740631b8ad2 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M util/sconfig/main.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/74594/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index aa79f1e..4562c6a 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1965,6 +1965,7 @@ fprintf(f, "#include <device/device.h>\n"); fprintf(f, "#include <device/pci.h>\n"); fprintf(f, "#include <fw_config.h>\n"); + fprintf(f, "#include <variant/gpio.h>\n"); fprintf(f, "#include <%s>\n", static_header); emit_chip_headers(f, chip_header.next); emit_identifiers(f, "struct device_operations", device_operations); -- To view, visit https://review.coreboot.org/c/coreboot/+/74594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia16211ef73fa9c6221f98c36879dd740631b8ad2 Gerrit-Change-Number: 74594 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/google/myst: Add named GPIO's
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74593 ) Change subject: mb/google/myst: Add named GPIO's ...................................................................... mb/google/myst: Add named GPIO's Add named GPIO's to help prevent confusion in GPIO management BUG=b:278969100 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed --- M src/mainboard/google/myst/chromeos.c M src/mainboard/google/myst/ec.c M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/myst/variants/myst/include/variant/gpio.h 7 files changed, 180 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74593/1 diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c index e488e81..5c10f65 100644 --- a/src/mainboard/google/myst/chromeos.c +++ b/src/mainboard/google/myst/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) {} diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/myst/ec.c index 060119d..d8c1ae3 100644 --- a/src/mainboard/google/myst/ec.c +++ b/src/mainboard/google/myst/ec.c @@ -3,9 +3,9 @@ #include <acpi/acpi.h> #include <amdblocks/smi.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/smi.h> #include <variant/ec.h> +#include <variant/gpio.h> static const struct sci_source espi_sci_sources[] = { { diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 0add7a0..4cdb4bc 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -1,171 +1,108 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <gpio.h> +#include <variant/gpio.h> /* GPIO configuration in ramstage*/ static const struct soc_amd_gpio base_gpio_table[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* Unused */ + PAD_NF(EC_SOC_PWR_BTN_ODL, PWR_BTN_L, PULL_NONE), + PAD_NF(SYS_RST_ODL, SYS_RESET_L, PULL_NONE), + PAD_NF_SCI(SOC_PCIE_WAKE_ODL, WAKE_L, PULL_NONE, EDGE_LOW), + /* GPIO_3 Unused */ PAD_NC(GPIO_3), - /* EN_PWR_FP */ - PAD_GPO(GPIO_4, LOW), - /* EN_PP3300_TCHPAD */ - PAD_GPO(GPIO_5, HIGH), - /* EN_PP3300_WWAN_X */ - PAD_GPO(GPIO_6, LOW), - /* SOC_PEN_DETECT_ODL */ - PAD_WAKE(GPIO_7, PULL_NONE, EDGE_LOW, S0i3), - /* SOC_TCHPAD_INT_ODL */ - PAD_SCI(GPIO_8, PULL_NONE, LEVEL_LOW), - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), - /* WWAN_RST */ - PAD_GPO(GPIO_11, LOW), - /* Unused */ + PAD_GPO(EN_PWR_FP, LOW), + PAD_GPO(EN_PP3300_TCHPAD_X, HIGH), + PAD_GPO(EN_PP3300_WWAN_X, LOW), + PAD_WAKE(SOC_PEN_DETECT_ODL, PULL_NONE, EDGE_LOW, S0i3), + PAD_SCI(SOC_TCHPAD_INT_ODL, PULL_NONE, LEVEL_LOW), + PAD_GPO(EN_PP3300_WLAN_X, HIGH), + PAD_GPO(WWAN_RST, LOW), + /* GPIO_12 Unused */ PAD_NC(GPIO_12), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* EC_SOC_WAKE_R_ODL */ - PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), - /* FP_SOC_INT_L */ - PAD_SCI(GPIO_18, PULL_NONE, LEVEL_LOW), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* Unused */ + PAD_NF(USB_FAULT_ODL, USB_OC0_L, PULL_NONE), + PAD_SCI(EC_SOC_WAKE_R_ODL, PULL_UP, EDGE_LOW), + PAD_SCI(FP_SOC_INT_L, PULL_NONE, LEVEL_LOW), + PAD_NF(I2C_SOC_AUDIO_HDMI_SCL_U, I2C3_SCL, PULL_NONE), + PAD_NF(I2C_SOC_AUDIO_HDMI_SDA_U, I2C3_SDA, PULL_NONE), + /* GPIO_21 Unused */ PAD_NC(GPIO_21), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_NONE), - /* Unused */ + PAD_NF(ESPI_EC_ALERT_SOC_ODL, ESPI_ALERT_D1, PULL_NONE), + PAD_NF(SOC_AC_PRES_OD, AC_PRES, PULL_NONE), + /* GPIO_24 Unused */ PAD_NC(GPIO_24), - /* GPIO_25-26: Not available */ - /* SOC_PCIE_RST1_R_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* GPIO_28: Not available */ - /* SD_AUX_RST */ - PAD_GPO(GPIO_29, LOW), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* SSD_AUX_RST */ - PAD_GPO(GPIO_31, LOW), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_37: Not available */ - /* WLAN_AUX_RST_L */ - PAD_GPO(GPIO_38, HIGH), - /* WWAN_AUX_RST_L */ - PAD_GPO(GPIO_39, HIGH), - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_40, HIGH), - /* GPIO_41 - GPIO_66: Not available */ - /* GPIO_67 (Unused) */ + PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH), + PAD_NFO(SOC_PCIE_RST1_R_L, PCIE_RST1_L, HIGH), + PAD_GPO(SD_AUX_RST, LOW), + PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE), + PAD_GPO(SSD_AUX_RST, LOW), + PAD_NF(LPC_RST_L_MB, LPC_RST_L, PULL_NONE), + PAD_GPO(WLAN_AUX_RST_L, HIGH), + PAD_GPO(WWAN_AUX_RST_L, HIGH), + PAD_GPO(SOC_FP_RST_L, HIGH), + PAD_GPI(SOC_MEM_VID_C1, PULL_NONE), + /* GPIO_67 Unused */ PAD_NC(GPIO_67), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SOC_CLK_FPMCU_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), - /* EN_TCHSCR_REPORT */ - PAD_GPO(GPIO_74, LOW), - /* SOC_CLK_FPMCU_R_L TODO(276939271): Selectively init */ - PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), - /* Unused */ + PAD_NF(ESPI_SOC_D2_EC_R, SPI1_DAT2, PULL_NONE), + PAD_NF(ESPI_SOC_D3_EC_R, SPI1_DAT3, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_CLK_FPMCU_R, SPI2_CLK, PULL_NONE), + PAD_GPO(EN_TCHSCR_REPORT, LOW), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_CS_FPMCU_R_L, SPI2_CS1_L, PULL_NONE), + /* GPIO_76 Unused */ PAD_NC(GPIO_76), - /* ESPI_SOC_CLK_EC_R */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* RAM_ID_0 */ - PAD_GPI(GPIO_78, PULL_NONE), - /* RAM_ID_1 */ - PAD_GPI(GPIO_79, PULL_NONE), - /* ESPI_SOC_D1_EC_R */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI_SOC_D0_EC_R */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ + PAD_NF(ESPI_SOC_CLK_EC_R, SPI1_CLK, PULL_NONE), + PAD_GPI(RAM_ID_0, PULL_NONE), + PAD_GPI(RAM_ID_1, PULL_NONE), + PAD_NF(ESPI_SOC_D1_EC_R, SPI1_DAT1, PULL_NONE), + PAD_NF(ESPI_SOC_D0_EC_R, SPI1_DAT0, PULL_NONE), + PAD_INT(GSC_SOC_INT_ODL, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* GPIO_85 Unused */ PAD_NC(GPIO_85), - /* HP_INT_ODL */ - PAD_GPI(GPIO_89, PULL_NONE), - /* EC_SOC_INT_ODL */ - PAD_GPI(GPIO_90, PULL_NONE), - /* TCHSCR_INT_ODL */ - PAD_GPI(GPIO_91, PULL_NONE), - /* CLK_REQ0_L / WLAN */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* SPI_SOC_DO_FPMCU_DI_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), - /* SPI_SOC_DI_FPMCU_DO_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), - /* RAM_ID_2 */ - PAD_GPI(GPIO_106, PULL_NONE), - /* RAM_ID_3 */ - PAD_GPI(GPIO_107, PULL_NONE), - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L / SD */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L / WWAN */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* Unused */ + PAD_GPI(HP_INT_ODL, PULL_NONE), + PAD_GPI(EC_SOC_INT_ODL, PULL_NONE), + PAD_GPI(TCHSCR_INT_ODL, PULL_NONE), + PAD_NF(PCIE_0_WLAN_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_DO_FPMCU_DI_R, SPI2_DAT0, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_DI_FPMCU_DO_R, SPI2_DAT1, PULL_NONE), + PAD_GPI(RAM_ID_2, PULL_NONE), + PAD_GPI(RAM_ID_3, PULL_NONE), + PAD_NF(I2C_SOC_GSC_SCL_U, I2C2_SCL, PULL_NONE), + PAD_NF(I2C_SOC_GSC_SDA_U, I2C2_SDA, PULL_NONE), + PAD_NF(PCIE_1_SD_CLKREQ_ODL, CLK_REQ1_L, PULL_NONE), + PAD_NF(PCIE_2_WWAN_CLKREQ_ODL, CLK_REQ2_L, PULL_NONE), + /* GPIO_130 Unused */ PAD_NC(GPIO_130), - /* CLK_REQ3_L / SSD */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* SOC_FP_BOOT0 */ - PAD_GPO(GPIO_132, LOW), - /* EN_PP3300_CAM */ - PAD_GPO(GPIO_135, HIGH), - /* Unused */ + PAD_NF(PCIE_3_SSD_CLKREQ_ODL, CLK_REQ3_L, PULL_NONE), + PAD_GPO(SOC_FP_BOOT0, LOW), + PAD_GPO(EN_PP3300_CAM_X, HIGH), + /* GPIO_136 Unused */ PAD_NC(GPIO_136), - /* Unused */ + /* GPIO_137 Unused */ PAD_NC(GPIO_137), - /* Unused */ + /* GPIO_138 Unused */ PAD_NC(GPIO_138), - /* SOC_BIOS_WP_OD */ - PAD_GPI(GPIO_139, PULL_NONE), - /* UART1_TXD / FPMCU TODO(276939271): Selectively init */ - PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), - /* UART0_RXD / DBG */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART1_RXD / FPMCU TODO(276939271): Selectively init */ - PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), - /* UART0_TXD / DBG */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_144, HIGH), - /* I2C0_SCL */ - PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), - /* I2C0_SDA */ - PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), - /* I2C1_SCL */ - PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), - /* I2C1_SDA */ - PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_153, LOW), - /* BT_DISABLE */ - PAD_GPO(GPIO_154, LOW), - /* HDMI_RST */ + PAD_GPI(SOC_BIOS_WP_OD, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(UART_SOC_TX_FPMCU_RX, UART1_TXD, PULL_NONE), + PAD_NF(UART_SOC_RX_DBG_TX, UART0_RXD, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(UART_SOC_RX_FPMCU_TX, UART1_RXD, PULL_NONE), + PAD_NF(UART_SOC_TX_DBG_RX, UART0_TXD, PULL_NONE), + PAD_GPO(EN_PP3300_TCHSCR_X, HIGH), + PAD_NF(I2C_SOC_TCHPAD_SCL, I2C0_SCL, PULL_NONE), + PAD_NF(I2C_SOC_TCHPAD_SDA, I2C0_SDA, PULL_NONE), + PAD_NF(I2C_SOC_TCHSCR_SCL, I2C1_SCL, PULL_NONE), + PAD_NF(I2C_SOC_TCHSCR_SDA, I2C1_SDA, PULL_NONE), + PAD_GPO(EN_SPKR, LOW), + PAD_GPO(BT_DISABLE, LOW), + /* GPIO_155 Unused */ PAD_GPO(GPIO_155, HIGH), - /* WLAN_DISABLE */ - PAD_GPO(GPIO_156, LOW), - /* TCHSCR_RST_L */ - PAD_GPO(GPIO_157, HIGH), + PAD_GPO(WLAN_DISABLE, LOW), + PAD_GPO(TCHSCR_RST_L, HIGH), }; /* GPIO configuration in bootblock */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h index c6ab30f..2eeb167 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h @@ -5,8 +5,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> -#include <gpio.h> +#include <variant/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ @@ -73,9 +72,6 @@ /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO -/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_90 - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h index a6683fd..13286b1 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h @@ -5,7 +5,78 @@ #include <gpio.h> +#define EC_SOC_PWR_BTN_ODL GPIO_0 +#define SYS_RST_ODL GPIO_1 +#define SOC_PCIE_WAKE_ODL GPIO_2 +#define EN_PWR_FP GPIO_4 +#define EN_PP3300_TCHPAD_X GPIO_5 +#define EN_PP3300_WWAN_X GPIO_6 +#define SOC_PEN_DETECT_ODL GPIO_7 +#define SOC_TCHPAD_INT_ODL GPIO_8 +#define EN_PP3300_WLAN_X GPIO_9 +#define WWAN_RST GPIO_11 +#define USB_FAULT_ODL GPIO_16 +#define EC_SOC_WAKE_R_ODL GPIO_17 +#define FP_SOC_INT_L GPIO_18 +#define I2C_SOC_AUDIO_HDMI_SCL_U GPIO_19 +#define I2C_SOC_AUDIO_HDMI_SDA_U GPIO_20 +#define ESPI_EC_ALERT_SOC_ODL GPIO_22 +#define SOC_AC_PRES_OD GPIO_23 +#define SOC_PCIE_RST0_R_L GPIO_26 +#define SOC_PCIE_RST1_R_L GPIO_27 +#define SD_AUX_RST GPIO_29 +#define ESPI_SOC_CS_EC_R_L GPIO_30 +#define SSD_AUX_RST GPIO_31 +#define LPC_RST_L_MB GPIO_32 +#define WLAN_AUX_RST_L GPIO_38 +#define WWAN_AUX_RST_L GPIO_39 +#define SOC_FP_RST_L GPIO_40 +#define SOC_MEM_VID_C1 GPIO_42 +#define ESPI_SOC_D2_EC_R GPIO_68 +#define ESPI_SOC_D3_EC_R GPIO_69 +#define SPI_SOC_CLK_FPMCU_R GPIO_70 +#define EN_TCHSCR_REPORT GPIO_74 +#define SPI_SOC_CS_FPMCU_R_L GPIO_75 +#define ESPI_SOC_CLK_EC_R GPIO_77 +#define RAM_ID_0 GPIO_78 +#define RAM_ID_1 GPIO_79 +#define ESPI_SOC_D1_EC_R GPIO_80 +#define ESPI_SOC_D0_EC_R GPIO_81 +#define GSC_SOC_INT_ODL GPIO_84 +#define HP_INT_ODL GPIO_89 +#define EC_SOC_INT_ODL GPIO_90 +#define TCHSCR_INT_ODL GPIO_91 +#define PCIE_0_WLAN_CLKREQ_ODL GPIO_92 +#define SPI_SOC_DO_FPMCU_DI_R GPIO_104 +#define SPI_SOC_DI_FPMCU_DO_R GPIO_105 +#define RAM_ID_2 GPIO_106 +#define RAM_ID_3 GPIO_107 +#define I2C_SOC_GSC_SCL_U GPIO_113 +#define I2C_SOC_GSC_SDA_U GPIO_114 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define PCIE_2_WWAN_CLKREQ_ODL GPIO_116 +#define PCIE_3_SSD_CLKREQ_ODL GPIO_131 +#define SOC_FP_BOOT0 GPIO_132 +#define EN_PP3300_CAM_X GPIO_135 +#define SOC_BIOS_WP_OD GPIO_139 +#define UART_SOC_TX_FPMCU_RX GPIO_140 +#define UART_SOC_RX_DBG_TX GPIO_141 +#define UART_SOC_RX_FPMCU_TX GPIO_142 +#define UART_SOC_TX_DBG_RX GPIO_143 +#define EN_PP3300_TCHSCR_X GPIO_144 +#define I2C_SOC_TCHPAD_SCL GPIO_145 +#define I2C_SOC_TCHPAD_SDA GPIO_146 +#define I2C_SOC_TCHSCR_SCL GPIO_147 +#define I2C_SOC_TCHSCR_SDA GPIO_148 +#define EN_SPKR GPIO_153 +#define BT_DISABLE GPIO_154 +#define WLAN_DISABLE GPIO_156 +#define TCHSCR_RST_L GPIO_157 + +/* EC sync irq */ +#define EC_SYNC_IRQ EC_SOC_INT_ODL + /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_139 +#define CROS_WP_GPIO SOC_BIOS_WP_OD #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 3f69548..a15a819 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <gpio.h> +#include <variant/gpio.h> /* This function provides base GPIO configuration table. */ diff --git a/src/mainboard/google/myst/variants/myst/include/variant/gpio.h b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/74593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed Gerrit-Change-Number: 74593 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74592 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... mb/google/skyrim: Add named GPIO's Add named GPIO's to help prevent confusion in GPIO management BUG=b:278968729 TEST=builds Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/skyrim/chromeos.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/skyrim/variants/baseboard/smihandler.c M src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c A src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h M src/mainboard/google/skyrim/variants/frostflow/gpio.c A src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/gpio.c A src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c A src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h M src/mainboard/google/skyrim/variants/winterhold/gpio.c A src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c M src/mainboard/google/skyrim/verstage.c 20 files changed, 229 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/74592/1 diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c index c65e045..d020c09 100644 --- a/src/mainboard/google/skyrim/chromeos.c +++ b/src/mainboard/google/skyrim/chromeos.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <bootmode.h> -#include <gpio.h> +#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c index f265cbf..82d3ba9 100644 --- a/src/mainboard/google/skyrim/ec.c +++ b/src/mainboard/google/skyrim/ec.c @@ -4,9 +4,9 @@ #include <amdblocks/smi.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/smi.h> #include <variant/ec.h> +#include <variant/gpio.h> static const struct sci_source espi_sci_sources[] = { { diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 80839a0..2e18d84 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_hotplug = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, - .gpio_group_id = GPIO_27, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ1, }, { /* SSD */ @@ -50,7 +50,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 969a995..bf80de4 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -1,208 +1,119 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <gpio.h> +#include <variant/gpio.h> /* GPIO configuration in ramstage*/ static const struct soc_amd_gpio base_gpio_table[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* SOC_PEN_DETECT_ODL */ - PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3), - /* EN_PWR_FP */ - PAD_GPO(GPIO_4, LOW), - /* EN_PP3300_TCHPAD */ - PAD_GPO(GPIO_5, HIGH), - /* SSD_AUX_RESET_L */ - PAD_GPO(GPIO_6, HIGH), - /* WLAN_AUX_RST_L */ - PAD_GPO(GPIO_7, HIGH), - /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, LOW), - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), - /* BT_DISABLE */ - PAD_GPO(GPIO_10, LOW), - /* EC_SOC_WAKE_ODL */ - PAD_SCI(GPIO_11, PULL_NONE, EDGE_LOW), - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_12, LOW), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* SOC_SAR_INT_L */ - PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* WLAN_DISABLE */ - PAD_GPO(GPIO_21, LOW), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_UP), - /* SOC_FP_INT_L */ - PAD_SCI(GPIO_24, PULL_NONE, LEVEL_LOW), - /* GPIO_25: Not available */ - /* PCIE_RST0_L */ - PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), - /* SD_AUX_RESET_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* GPIO_28: Not available */ - /* TCHSCR_INT_ODL */ - PAD_GPI(GPIO_29, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* Unused */ + PAD_NF(SOC_PWR_BTN_L, PWR_BTN_L, PULL_NONE), + PAD_NF(SYS_RST_ODL, SYS_RESET_L, PULL_NONE), + PAD_NF_SCI(SOC_PCIE_WAKE_L, WAKE_L, PULL_NONE, EDGE_LOW), + PAD_WAKE(SOC_PEN_DETECT_ODL, PULL_NONE, EDGE_LOW, S0i3), + PAD_GPO(EN_PWR_FP, LOW), + PAD_GPO(EN_PP3300_TCHPAD, HIGH), + PAD_GPO(SSD_AUX_RST_L, HIGH), + PAD_GPO(WLAN_AUX_RST_L, HIGH), + PAD_GPO(EN_PWR_WWAN_X, LOW), + PAD_GPO(EN_PP3300_WLAN, HIGH), + PAD_GPO(BT_DISABLE, LOW), + PAD_SCI(EC_SOC_WAKE_ODL, PULL_NONE, EDGE_LOW), + PAD_GPO(SOC_FP_RST_L, LOW), + PAD_NF(USB_FAULT_R_ODL, USB_OC0_L, PULL_NONE), + PAD_SCI(SOC_SAR_INT_R_L, PULL_NONE, EDGE_LOW), + PAD_INT(GSC_SOC_INT_L, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + PAD_NF(SOC_I2C_3_SCL, I2C3_SCL, PULL_NONE), + PAD_NF(SOC_I2C_3_SDA, I2C3_SDA, PULL_NONE), + PAD_GPO(WLAN_DISABLE, LOW), + PAD_NF(ESPI_EC_ALERT_SOC_R_ODL, ESPI_ALERT_D1, PULL_NONE), + PAD_NF(SOC_AC_PRES, AC_PRES, PULL_UP), + PAD_SCI(SOC_FP_INT_L, PULL_NONE, LEVEL_LOW), + PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH), + PAD_NFO(SD_AUX_RST_SOC_L, PCIE_RST1_L, HIGH), + PAD_GPI(TCHSCR_INT_ODL, PULL_NONE), + PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE), + /* GPIO_31 Unused */ PAD_NC(GPIO_31), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_39: Not available */ - /* SOC_TCHPAD_INT_ODL */ - PAD_SCI(GPIO_40, PULL_NONE, LEVEL_LOW), - /* GPIO_41: Not available */ - /* WWAN_RST_L */ - PAD_GPO(GPIO_42, HIGH), - /* GPIO_43 - GPIO_66: Not available */ - /* GPIO_67 (Unused) */ + PAD_NF(LPC_RST_L_MB, LPC_RST_L, PULL_NONE), + PAD_SCI(SOC_TCHPAD_INT_ODL, PULL_NONE, LEVEL_LOW), + PAD_GPO(WWAN_RST, HIGH), + /* GPIO_67 Unused */ PAD_NC(GPIO_67), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SOC_DISABLE_DISP_BL */ - PAD_GPO(GPIO_74, LOW), - /* TCHSCR_REPORT_EN */ - PAD_GPO(GPIO_76, LOW), - /* ESPI_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* EN_PP3300_CAM */ - PAD_GPO(GPIO_78, HIGH), - /* ESPI1_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI1_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* EC_SOC_INT_ODL */ - PAD_GPI(GPIO_84, PULL_NONE), - /* RAM_ID_1 / DEV_BEEP_DATA */ - PAD_GPI(GPIO_85, PULL_NONE), - /* RAM_ID_2 / DEV_BEEP_LRCLK */ - PAD_GPI(GPIO_89, PULL_NONE), - /* HP_INT_ODL */ - PAD_GPI(GPIO_90, PULL_NONE), - /* RAM_ID_3 / DEV_BEEP_BCLK */ - PAD_GPI(GPIO_91, PULL_NONE), - /* CLK_REQ0_L / SSD */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L / SD */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L / WLAN */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* SOC_FPMCU_BOOT0 */ - PAD_GPO(GPIO_130, LOW), - /* Enable touchscreen, release from reset */ - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_131, HIGH), - /* TCHSCR_RESET_L */ - PAD_GPO(GPIO_136, HIGH), - /* SOC_BIOS_WP_L */ - PAD_GPI(GPIO_138, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_139, LOW), - /* RAM_ID_0 / DEV_BEEP_EN */ - PAD_GPI(GPIO_144, PULL_NONE), - /* UART1_TXD / FP */ - PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), - /* UART0_RXD / DBG */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART1_RXD / FP*/ - PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), - /* UART0_TXD / DBG */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* I2C0_SCL */ - PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), - /* I2C0_SDA */ - PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), - /* I2C1_SCL */ - PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), - /* I2C1_SDA */ - PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + PAD_NF(ESPI_SOC_D2_R, SPI1_DAT2, PULL_NONE), + PAD_NF(ESPI_SOC_D3_R, SPI1_DAT3, PULL_NONE), + PAD_GPO(SOC_DISABLE_DISP_BL_R, LOW), + PAD_GPO(TCHSCR_REPORT_EN, LOW), + PAD_NF(ESPI_SOC_CLK_R, SPI1_CLK, PULL_NONE), + PAD_GPO(EN_PP3300_CAM, HIGH), + PAD_NF(ESPI_SOC_D1_R, SPI1_DAT1, PULL_NONE), + PAD_NF(ESPI_SOC_D0_R, SPI1_DAT0, PULL_NONE), + PAD_GPI(EC_SOC_INT_ODL, PULL_NONE), + PAD_GPI(RAM_ID_1, PULL_NONE), + PAD_GPI(RAM_ID_2, PULL_NONE), + PAD_GPI(HP_INT_ODL, PULL_NONE), + PAD_GPI(RAM_ID_3, PULL_NONE), + PAD_NF(PCIE_0_SSD_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE), + PAD_NF(SOC_I2C_2_SCL, I2C2_SCL, PULL_NONE), + PAD_NF(SOC_I2C_2_SDA, I2C2_SDA, PULL_NONE), + PAD_NF(PCIE_1_SD_CLKREQ_ODL, CLK_REQ1_L, PULL_NONE), + PAD_NF(PCIE_2_WLAN_CLKREQ_ODL, CLK_REQ2_L, PULL_NONE), + PAD_GPO(SOC_FPMCU_BOOT0, LOW), + PAD_GPO(EN_PP3300_TCHSCR, HIGH), + PAD_GPO(TCHSCR_RST_L, HIGH), + PAD_GPI(SOC_BIOS_WP_L, PULL_NONE), + PAD_GPO(EN_SPKR, LOW), + PAD_GPI(RAM_ID_0, PULL_NONE), + PAD_NF(UART_SOC_TX_FP_RX, UART1_TXD, PULL_NONE), + PAD_NF(UART_DBG_TX_SOC_RX_R, UART0_RXD, PULL_NONE), + PAD_NF(UART_FP_TX_SOC_RX, UART1_RXD, PULL_NONE), + PAD_NF(UART_SOC_TX_DBG_RX_R, UART0_TXD, PULL_NONE), + PAD_NF(SOC_I2C_0_SCL, I2C0_SCL, PULL_NONE), + PAD_NF(SOC_I2C_0_SDA, I2C0_SDA, PULL_NONE), + PAD_NF(SOC_I2C_1_SCL, I2C1_SCL, PULL_NONE), + PAD_NF(SOC_I2C_1_SDA, I2C1_SDA, PULL_NONE), }; static const struct soc_amd_gpio espi_gpio_table[] = { - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_CLK */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* ESPI1_DATA0 */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* ESPI1_DATA1 */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE), + PAD_NF(ESPI_SOC_CLK_R, SPI1_CLK, PULL_NONE), + PAD_NF(ESPI_SOC_D0_R, SPI1_DAT0, PULL_NONE), + PAD_NF(ESPI_SOC_D1_R, SPI1_DAT1, PULL_NONE), + PAD_NF(ESPI_SOC_D2_R, SPI1_DAT2, PULL_NONE), + PAD_NF(ESPI_SOC_D3_R, SPI1_DAT3, PULL_NONE), + PAD_NF(ESPI_EC_ALERT_SOC_R_ODL, ESPI_ALERT_D1, PULL_NONE), }; static const struct soc_amd_gpio tpm_gpio_table[] = { - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + PAD_NF(SOC_I2C_3_SCL, I2C3_SCL, PULL_NONE), + PAD_NF(SOC_I2C_3_SDA, I2C3_SDA, PULL_NONE), + PAD_INT(GSC_SOC_INT_L, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), }; /* GPIO configuration in bootblock */ static const struct soc_amd_gpio bootblock_gpio_table[] = { /* Enable WLAN */ - /* WLAN_DISABLE */ - PAD_GPO(GPIO_21, LOW), + PAD_GPO(WLAN_DISABLE, LOW), }; /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { - /* WLAN_AUX_RESET_L (ACTIVE LOW) */ - PAD_GPO(GPIO_7, LOW), + PAD_GPO(WLAN_AUX_RST_L, LOW), /* Power on WLAN */ - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), + PAD_GPO(EN_PP3300_WLAN, HIGH), }; /* Romstage GPIO configuration */ static const struct soc_amd_gpio romstage_gpio_table[] = { /* PCIE_RST needs to be brought high before FSP-M runs */ /* Deassert all AUX_RESET lines & PCIE_RST */ - /* WLAN_AUX_RESET_L (ACTIVE LOW) */ - PAD_GPO(GPIO_7, HIGH), - /* PCIE_RST0_L */ - PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), - /* SD_AUX_RESET_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* SSD_AUX_RESET_L */ - PAD_GPO(GPIO_6, HIGH), - /* CLK_REQ0_L / SSD */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + PAD_GPO(WLAN_AUX_RST_L, HIGH), + PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH), + PAD_NFO(SD_AUX_RST_SOC_L, PCIE_RST1_L, HIGH), + PAD_GPO(SSD_AUX_RST_L, HIGH), + PAD_NF(PCIE_0_SSD_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE), /* Enable touchscreen, hold in reset */ - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_131, HIGH), - /* TCHSCR_RESET_L */ - PAD_GPO(GPIO_136, LOW), + PAD_GPO(EN_PP3300_TCHSCR, HIGH), + PAD_GPO(TCHSCR_RST_L, LOW), }; void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h index c04cc5b..bc2f334 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -5,8 +5,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> -#include <gpio.h> +#include <variant/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ @@ -73,9 +72,6 @@ /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO -/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_84 - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h index eb17eff..24244cb 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h @@ -5,7 +5,73 @@ #include <gpio.h> +#define SOC_PWR_BTN_L GPIO_0 +#define SYS_RST_ODL GPIO_1 +#define SOC_PCIE_WAKE_L GPIO_2 +#define SOC_PEN_DETECT_ODL GPIO_3 +#define EN_PWR_FP GPIO_4 +#define EN_PP3300_TCHPAD GPIO_5 +#define SSD_AUX_RST_L GPIO_6 +#define WLAN_AUX_RST_L GPIO_7 +#define EN_PWR_WWAN_X GPIO_8 +#define EN_PP3300_WLAN GPIO_9 +#define BT_DISABLE GPIO_10 +#define EC_SOC_WAKE_ODL GPIO_11 +#define SOC_FP_RST_L GPIO_12 +#define USB_FAULT_R_ODL GPIO_16 +#define SOC_SAR_INT_R_L GPIO_17 +#define GSC_SOC_INT_L GPIO_18 +#define SOC_I2C_3_SCL GPIO_19 +#define SOC_I2C_3_SDA GPIO_20 +#define WLAN_DISABLE GPIO_21 +#define ESPI_EC_ALERT_SOC_R_ODL GPIO_22 +#define SOC_AC_PRES GPIO_23 +#define SOC_FP_INT_L GPIO_24 +#define SOC_PCIE_RST0_R_L GPIO_26 +#define SD_AUX_RST_SOC_L GPIO_27 +#define TCHSCR_INT_ODL GPIO_29 +#define ESPI_SOC_CS_EC_R_L GPIO_30 +#define LPC_RST_L_MB GPIO_32 +#define SOC_TCHPAD_INT_ODL GPIO_40 +#define WWAN_RST GPIO_42 +#define SOC_TDP_STRAP GPIO_67 +#define ESPI_SOC_D2_R GPIO_68 +#define ESPI_SOC_D3_R GPIO_69 +#define SOC_DISABLE_DISP_BL_R GPIO_74 +#define TCHSCR_REPORT_EN GPIO_76 +#define ESPI_SOC_CLK_R GPIO_77 +#define EN_PP3300_CAM GPIO_78 +#define ESPI_SOC_D1_R GPIO_80 +#define ESPI_SOC_D0_R GPIO_81 +#define EC_SOC_INT_ODL GPIO_84 +#define RAM_ID_1 GPIO_85 +#define RAM_ID_2 GPIO_89 +#define HP_INT_ODL GPIO_90 +#define RAM_ID_3 GPIO_91 +#define PCIE_0_SSD_CLKREQ_ODL GPIO_92 +#define SOC_I2C_2_SCL GPIO_113 +#define SOC_I2C_2_SDA GPIO_114 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define PCIE_2_WLAN_CLKREQ_ODL GPIO_116 +#define SOC_FPMCU_BOOT0 GPIO_130 +#define EN_PP3300_TCHSCR GPIO_131 +#define TCHSCR_RST_L GPIO_136 +#define SOC_BIOS_WP_L GPIO_138 +#define EN_SPKR GPIO_139 +#define UART_SOC_TX_FP_RX GPIO_140 +#define UART_DBG_TX_SOC_RX_R GPIO_141 +#define UART_FP_TX_SOC_RX GPIO_142 +#define UART_SOC_TX_DBG_RX_R GPIO_143 +#define RAM_ID_0 GPIO_144 +#define SOC_I2C_0_SCL GPIO_145 +#define SOC_I2C_0_SDA GPIO_146 +#define SOC_I2C_1_SCL GPIO_147 +#define SOC_I2C_1_SDA GPIO_148 + /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_138 +#define CROS_WP_GPIO SOC_BIOS_WP_L + +/* EC sync irq */ +#define EC_SYNC_IRQ EC_SOC_INT_ODL #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index e49b7c4..bb7c349 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <gpio.h> +#include <variant/gpio.h> #include <soc/pci_devs.h> #include <platform_descriptors.h> diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c index ff59b2b..a6aa1ba 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c +++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c @@ -6,8 +6,8 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> -#include <gpio.h> #include <variant/ec.h> +#include <variant/gpio.h> void mainboard_smi_sleep(u8 slp_typ) { diff --git a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c index 7e513ef..645fd6a 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <security/tpm/tis.h> -#include <gpio.h> +#include <variant/gpio.h> int tis_plat_irq_status(void) { - return gpio_interrupt_status(GPIO_18); + return gpio_interrupt_status(GSC_SOC_INT_L); } diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/frostflow/gpio.c b/src/mainboard/google/skyrim/variants/frostflow/gpio.c index 45ead98..fb9c6ac 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/gpio.c +++ b/src/mainboard/google/skyrim/variants/frostflow/gpio.c @@ -1,17 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <gpio.h> +#include <variant/gpio.h> /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - /* EN_PWR_WWAN_X => CAM_PSW_L */ - PAD_INT(GPIO_8, PULL_NONE, BOTH_EDGES, STATUS_DELIVERY), - /* SOC_SAR_INT_L => Unused */ + PAD_INT(CAM_PSW_L, PULL_NONE, BOTH_EDGES, STATUS_DELIVERY), + /* SOC_SAR_INT_L(GPIO_17) => Unused */ PAD_NC(GPIO_17), - /* WWAN_RST_L => Unused */ + /* WWAN_RST(GPIO_42) => Unused */ PAD_NC(GPIO_42), }; diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h new file mode 100644 index 0000000..8ef9f3a --- /dev/null +++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> + +/* EN_PWR_WWAN_X(GPIO_8) => CAM_PSW_L */ +#define CAM_PSW_L GPIO_8 + +/* SOC_SAR_INT_L(GPIO_17) => Unused */ +/* WWAN_RST(GPIO_42) => Unused */ \ No newline at end of file diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c index 9753179..a7dff10 100644 --- a/src/mainboard/google/skyrim/variants/markarth/gpio.c +++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c @@ -1,22 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> + #include <baseboard/variants.h> -#include <gpio.h> +#include <variant/gpio.h> /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - /* SOC_PEN_DETECT_ODL => Unused */ + /* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */ PAD_NC(GPIO_3), - /* EN_PWR_FP => Unused */ + /* EN_PWR_FP(GPIO_4) => Unused */ PAD_NC(GPIO_4), - /* EN_PWR_WWAN_X => Unused */ + /* EN_PWR_WWAN_X(GPIO_8) => Unused */ PAD_NC(GPIO_8), - /* SOC_FP_INT_L => Unused */ + /* SOC_FP_INT_L(GPIO_24) => Unused */ PAD_NC(GPIO_24), - /* SD_AUX_RST_SOC_L => Unused */ + /* SD_AUX_RST_SOC_L(GPIO_27) => Unused */ PAD_NC(GPIO_27), - /* WWAN_RST_L => Unused */ + /* WWAN_RST(GPIO_42) => Unused */ PAD_NC(GPIO_42), }; diff --git a/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h new file mode 100644 index 0000000..f30a952 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> + +/* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */ +/* EN_PWR_FP(GPIO_4) => Unused */ +/* EN_PWR_WWAN_X(GPIO_8) => Unused */ +/* SOC_FP_INT_L(GPIO_24) => Unused */ +/* SD_AUX_RST_SOC_L(GPIO_27) => Unused */ +/* WWAN_RST(GPIO_42) => Unused */ \ No newline at end of file diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 330fc46..9e2702f 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ1, }, }; @@ -69,7 +69,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/winterhold/gpio.c b/src/mainboard/google/skyrim/variants/winterhold/gpio.c index 340bfb6..f8fa98b 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/gpio.c +++ b/src/mainboard/google/skyrim/variants/winterhold/gpio.c @@ -1,22 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> + #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <gpio.h> +#include <variant/gpio.h> /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - /* SOC_PEN_DETECT_ODL */ + /* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */ PAD_NC(GPIO_3), - - /* EN_PWR_WWAN_X */ + /* EN_PWR_WWAN_X(GPIO_8) => Unused */ PAD_NC(GPIO_8), - - /* SD_AUX_RST_SOC_L */ + /* SD_AUX_RST_SOC_L(GPIO_27) => Unused */ PAD_NC(GPIO_27), - - /* WWAN_RST_L */ + /* WWAN_RST(GPIO_42) => Unused */ PAD_NC(GPIO_42), }; diff --git a/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c index 330fc46..9e2702f 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ1, }, }; @@ -69,7 +69,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/verstage.c b/src/mainboard/google/skyrim/verstage.c index 1079e9b..8a9a2cc 100644 --- a/src/mainboard/google/skyrim/verstage.c +++ b/src/mainboard/google/skyrim/verstage.c @@ -3,11 +3,11 @@ #include <amdblocks/acpimmio.h> #include <arch/io.h> #include <baseboard/variants.h> -#include <gpio.h> #include <psp_verstage.h> #include <security/vboot/vboot_common.h> #include <soc/espi.h> #include <soc/southbridge.h> +#include <variant/gpio.h> void verstage_mainboard_early_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Gerrit-Change-Number: 74592 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd/common: Update GPIO macros
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74591 ) Change subject: soc/amd/common: Update GPIO macros ...................................................................... soc/amd/common: Update GPIO macros Update GPIO macros to accommodate multiple levels of indirection with GPIO naming. This will allow individual programs to #define net/signal names to GPIO_NN names for use in their own development. Enabling projects to rename their own GPIOs to nets will hopefully make the code more readable and obvious, and prevent translation mistakes in reading GPIO numbers from schematics. BUG=b:278969100, b:278968729 TEST=builds Change-Id: I918d659eecf2076ed9089218177874ed2c9023b3 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/soc/amd/common/block/include/amdblocks/gpio_defs.h 1 file changed, 39 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74591/1 diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index c5aa3f1..819461f 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -205,64 +205,71 @@ #define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake #define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb +#define CREATE_FUNC(pin, func) CREATE_FUNC_INNER(pin, func) +#define CREATE_FUNC_INNER(pin, func) GPIO_ ## pin ## _IOMUX_ ## func + /* Native function pad configuration with PAD_PULL */ #define PAD_NF(pin, func, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, func), PAD_PULL(pull)) /* Native function pad configuration with PAD_OUTPUT */ #define PAD_NFO(pin, func, direction) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_OUTPUT(direction)) + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, func), PAD_OUTPUT(direction)) + +/* Native function pad configuration with PAD_OUTPUT from named GPIO */ +#define PAD_NFO_NAMED(pin, func, direction) \ + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, func), PAD_OUTPUT(direction)) /* General purpose input pad configuration */ #define PAD_GPI(pin, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), PAD_PULL(pull)) /* General purpose output pad configuration */ #define PAD_GPO(pin, direction) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), PAD_OUTPUT(direction)) /* Legacy interrupt pad configuration */ #define PAD_INT(pin, pull, trigger, action) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) /* SCI pad configuration */ #define PAD_SCI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT_FLAGS(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) /* SMI pad configuration */ #define PAD_SMI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT_FLAGS(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) /* Native function + SCI pad configuration */ #define PAD_NF_SCI(pin, func, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_ ## func, \ + PAD_CFG_STRUCT_FLAGS(pin, CREATE_FUNC(pin, func), \ PAD_PULL(pull), \ PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) /* WAKE pad configuration */ #define PAD_WAKE(pin, pull, trigger, type) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) /* pin debounce configuration */ #define PAD_DEBOUNCE(pin, pull, type, time) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) /* Wake + debounce configuration */ #define PAD_WAKE_DEBOUNCE(pin, pull, trigger, waketype, debtype, time) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), \ PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(waketype) | \ PAD_DEBOUNCE_CONFIG(debtype) | PAD_DEBOUNCE_CONFIG(time)) /* No-connect pad - configured as input with PULL_DOWN */ #define PAD_NC(pin) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) + PAD_CFG_STRUCT(pin, CREATE_FUNC(pin, GPIOxx), PAD_PULL(PULL_DOWN)) #define GEVENT_0 0 #define GEVENT_1 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918d659eecf2076ed9089218177874ed2c9023b3 Gerrit-Change-Number: 74591 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL
by Sridhar Siricilla (Code Review) 20 Apr '23

20 Apr '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74578 ) Change subject: soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL ...................................................................... soc/intel/mtl: [TEST] Read R_DCI_PCR_ECTRL Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie2f52acfadc44307b91a7528e5d796ddeef5ed1d --- M src/soc/intel/meteorlake/bootblock/soc_die.c M src/soc/intel/meteorlake/include/soc/pcr_ids.h 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74578/1 diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c index f5a3c91..3c44025 100644 --- a/src/soc/intel/meteorlake/bootblock/soc_die.c +++ b/src/soc/intel/meteorlake/bootblock/soc_die.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> @@ -136,6 +137,12 @@ } } +#define R_DCI_PCR_ECTRL 0x00000004 +static void dci_log_dbgctrl(void) +{ + printk(BIOS_DEBUG, "R_DCI_PCR_ECTRL 0x%x\n", pcr_read32(PID_DCI, R_DCI_PCR_ECTRL); +} + void bootblock_soc_die_init(void) { /* @@ -151,4 +158,7 @@ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + + + dci_log_dbgctrl(); } diff --git a/src/soc/intel/meteorlake/include/soc/pcr_ids.h b/src/soc/intel/meteorlake/include/soc/pcr_ids.h index 0ef9f30..819fa55 100644 --- a/src/soc/intel/meteorlake/include/soc/pcr_ids.h +++ b/src/soc/intel/meteorlake/include/soc/pcr_ids.h @@ -28,5 +28,6 @@ #define PID_ISCLK 0x64 #define PID_DMI 0x88 #define PID_IOM 0xAA +#define PID_DCI 0xCF #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2f52acfadc44307b91a7528e5d796ddeef5ed1d Gerrit-Change-Number: 74578 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Add or remove brackets
by Yu-Ping Wu (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Arthur Heymans. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74545 ) Change subject: vendorcode/mediatek/mt8192: Add or remove brackets ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Gerrit-Change-Number: 74545 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 20 Apr 2023 03:09:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8183: Fix set but unused variable
by Yu-Ping Wu (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74554 ) Change subject: soc/mediatek/mt8183: Fix set but unused variable ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686 Gerrit-Change-Number: 74554 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 02:44:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Cast enum types
by Yidi Lin (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Arthur Heymans. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74546 ) Change subject: vendorcode/mediatek/mt8192: Cast enum types ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Gerrit-Change-Number: 74546 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 20 Apr 2023 02:37:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Add or remove brackets
by Yidi Lin (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Arthur Heymans, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74545 ) Change subject: vendorcode/mediatek/mt8192: Add or remove brackets ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Gerrit-Change-Number: 74545 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 02:36:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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