coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Michał Żygowski (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 23: (4 comments) Patchset: PS22: > Corrected, regarding notes. Ack File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/25d93af8_52679189 PS22, Line 461: PCIe vGPIO > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/9574ca94_48ee2c64 PS22, Line 483: GPP_SYS_VGPIO_USB > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/0261a690_3ec852d9 PS22, Line 536: vGPIO_PADDING > Done Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 23 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Apr 2023 07:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74582 to look at the new patch set (#2). Change subject: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function ...................................................................... soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/meteorlake/romstage/romstage.c 3 files changed, 28 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74582/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Gerrit-Change-Number: 74582 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks
by Tony Huang (Code Review) 20 Apr '23

20 Apr '23

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74584 ) Change subject: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks ...................................................................... mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks Yavilla board memory id setting references to yaviks. This CL aligen it with yaviks. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) H58G56BK7BX068 3 (0011) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc M src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt 3 files changed, 50 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/74584/1 diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc index a0e6c21..82e3814 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc @@ -5,5 +5,8 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT -SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070 diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt index 598edff..425762c 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt @@ -5,10 +5,14 @@ DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) -H58G56BK7BX068 1 (0001) -MT62F1G32D2DS-026 WT:B 1 (0001) -K3KL8L80CM-MGCT 1 (0001) -H58G66BK7BX067 2 (0010) -MT62F2G32D4DS-026 WT:B 2 (0010) -K3KL9L90CM-MGCT 2 (0010) +H58G56AK6BX069 2 (0010) +K3LKBKB0BM-MGCP 2 (0010) +H58G56BK7BX068 3 (0011) +MT62F1G32D2DS-026 WT:B 3 (0011) +K3KL8L80CM-MGCT 3 (0011) +H58G66BK7BX067 4 (0100) +MT62F2G32D4DS-026 WT:B 4 (0100) +K3KL9L90CM-MGCT 4 (0100) +H58G66AK6BX070 5 (0101) diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt index 5ef4186..607026b 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt @@ -10,10 +10,14 @@ # Part Name MT62F512M32D2DR-031 WT:B +MT62F1G32D4DR-031 WT:B H9JCNNNBK3MLYR-N6E +H58G56AK6BX069 +K3LKBKB0BM-MGCP H58G56BK7BX068 MT62F1G32D2DS-026 WT:B K3KL8L80CM-MGCT H58G66BK7BX067 MT62F2G32D4DS-026 WT:B K3KL9L90CM-MGCT +H58G66AK6BX070 -- To view, visit https://review.coreboot.org/c/coreboot/+/74584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Gerrit-Change-Number: 74584 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
by John Su (Code Review) 20 Apr '23

20 Apr '23

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74583 ) Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead ...................................................................... mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead Because WD SSD drive isn't holding the clock low for some reason. So we chage to read eMMc clkreq signal instead. BRANCH=none BUG=b:278495684 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e --- M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c 1 file changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74583/1 diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 330fc46..94eb465 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -74,7 +74,7 @@ }, }; -#define NVME_CLKREQ_GPIO 92 +#define EMMC_CLKREQ_GPIO 115 void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) { /* @@ -85,13 +85,13 @@ * This allows checking the state of the NVMe device clkreq signal and enabling * either eMMC or NVMe based on that. */ - if (gpio_get(NVME_CLKREQ_GPIO)) { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); - *dxio_descs = emmc_dxio_descriptors; - } else { + if (gpio_get(EMMC_CLKREQ_GPIO)) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); *dxio_descs = nvme_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Gerrit-Change-Number: 74583 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Tarun Tuli, Kangheui Won, Kapil Porwal, Dinesh Gehlot. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Tarun Tuli, Kangheui Won, Kapil Porwal, Dinesh Gehlot, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74532 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override ...................................................................... soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 --- M src/soc/intel/alderlake/chip.c 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/74532/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Gerrit-Change-Number: 74532 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has uploaded a new patch set (#24) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74208 ) Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM ...................................................................... soc/intel/cmn/cse: Store ISH firmware version into CBMEM The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 24 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: lib: Perform early initialization of FW config in ramstage
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74530 ) Change subject: lib: Perform early initialization of FW config in ramstage ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36e7c7d2edc74a2b7fcc192690af73651e87183 Gerrit-Change-Number: 74530 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Kangheui Won, Dinesh Gehlot, Sridhar Siricilla, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... Patch Set 19: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74256/comment/64023161_6ddc1741 PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { : timestamp_add_now(TS_CSE_FW_SYNC_START); : cse_fw_sync(); : timestamp_add_now(TS_CSE_FW_SYNC_END); : : if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) : store_cse_rw_fw_version(); : } : } > > @Arthur, would you mind to take a look into this cl and share your comments based on the above res […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 19 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 20 Apr 2023 06:04:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Subrata Banik (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kangheui Won, Dinesh Gehlot, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#20) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. Additionally, this patch adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 128 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 20 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common: Update GPIO macros
by Jon Murphy (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Mark Hasemeyer, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74591 ) Change subject: soc/amd/common: Update GPIO macros ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Made an assumption that the value of the GPIO would match the macro name. Need to rethink how to handle this. -- To view, visit https://review.coreboot.org/c/coreboot/+/74591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918d659eecf2076ed9089218177874ed2c9023b3 Gerrit-Change-Number: 74591 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 05:55:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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