coreboot-gerrit April 2023

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[M] Change in coreboot[master]: vendorcode/mediatek/mt8192: Fix set but unused variables
by Xixi Chen (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Arthur Heymans, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74544 ) Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Gerrit-Change-Number: 74544 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 13:08:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
by Chao Gui (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: John Su, Jason Nien, Jon Murphy, Jason Glenesk, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74583 ) Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Gerrit-Change-Number: 74583 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 13:07:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
by Chao Gui (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: John Su, Jason Nien, Jon Murphy, Jason Glenesk, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74583 ) Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: nit: typo in commit message: So we `chage` to... -- To view, visit https://review.coreboot.org/c/coreboot/+/74583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Gerrit-Change-Number: 74583 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 13:06:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function
by Arthur Heymans (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Tarun Tuli, Subrata Banik, Kangheui Won, Kapil Porwal. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74582 ) Change subject: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Gerrit-Change-Number: 74582 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 12:58:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Refactor ramstage cse fw sync() function
by Arthur Heymans (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Tarun Tuli, Subrata Banik, Kangheui Won, Kapil Porwal. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74581 ) Change subject: soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Gerrit-Change-Number: 74581 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 12:57:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vendorcode/mediatek/mt8192: Fix set but unused variables
by Paul Menzel (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Arthur Heymans, Xixi Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74544 ) Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74544/comment/37cc3cfc_ecafe77f PS5, Line 9: BUILD_TIMELESS > > What's this?Means build faster? […] … and no commit hash (which can also be considered a (transformed/indirect) timestamp). -- To view, visit https://review.coreboot.org/c/coreboot/+/74544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Gerrit-Change-Number: 74544 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 12:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/birman: Enable PCIe RTD3 support
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74247 ) Change subject: mb/amd/birman: Enable PCIe RTD3 support ...................................................................... mb/amd/birman: Enable PCIe RTD3 support Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/devicetree_phoenix.cb 2 files changed, 30 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index d27c38b..5d297da 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -8,6 +8,7 @@ select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select AMD_SOC_CONSOLE_UART if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE select MAINBOARD_HAS_CHROMEOS select PCIEXP_ASPM select PCIEXP_CLK_PM diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index ff54e1f..2fc78aa 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -162,12 +162,24 @@ device domain 0 on device ref iommu on end device ref gpp_bridge_1_1 on end # MXM - device ref gpp_bridge_1_2 on end # NVMe SSD1 + device ref gpp_bridge_1_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD1 device ref gpp_bridge_1_3 on end # GBE device ref gpp_bridge_2_1 on end # SD device ref gpp_bridge_2_2 on end # WWAN device ref gpp_bridge_2_3 on end # WIFI - device ref gpp_bridge_2_4 on end # NVMe SSD0 + device ref gpp_bridge_2_4 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD0 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) -- To view, visit https://review.coreboot.org/c/coreboot/+/74247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 Gerrit-Change-Number: 74247 Gerrit-PatchSet: 8 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg
by Arthur Heymans (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Matt DeVillier, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74567 ) Change subject: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Gerrit-Change-Number: 74567 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 12:45:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/birman: Update DXIO descriptors per schematic
by Felix Held (Code Review) 20 Apr '23

20 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69705 ) Change subject: mb/amd/birman: Update DXIO descriptors per schematic ...................................................................... mb/amd/birman: Update DXIO descriptors per schematic Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7 Update devicetree to reference the updated DXIO descriptors. TEST=boot birman and note the devices show up in the logs correctly Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/birman/port_descriptors_phoenix.c 2 files changed, 199 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 9cebaab..ff54e1f 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -151,16 +151,23 @@ .PhyP3CpmP4Support = 0, }" - register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" - register "gpp_clk_config[2]" = "GPP_CLK_OFF" - register "gpp_clk_config[3]" = "GPP_CLK_REQ" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # MXM + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # NVMe SSD1 + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVMe SSD0 + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # WWAN + register "gpp_clk_config[5]" = "GPP_CLK_REQ" # SD + register "gpp_clk_config[6]" = "GPP_CLK_REQ" # GBE device domain 0 on device ref iommu on end - device ref gpp_bridge_2_1 on end # GBE - device ref gpp_bridge_2_2 on end # WIFI - device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_1_1 on end # MXM + device ref gpp_bridge_1_2 on end # NVMe SSD1 + device ref gpp_bridge_1_3 on end # GBE + device ref gpp_bridge_2_1 on end # SD + device ref gpp_bridge_2_2 on end # WWAN + device ref gpp_bridge_2_3 on end # WIFI + device ref gpp_bridge_2_4 on end # NVMe SSD0 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index df961bf..d254eea 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -4,52 +4,136 @@ #include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> +#include <soc/soc_util.h> #include <types.h> -/* TODO: Update for birman */ +#define phx_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 7, \ + .device_number = 1, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ0, \ +} -static const fsp_dxio_descriptor birman_dxio_descriptors[] = { - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, - .function_number = 1, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ3, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 2, - .function_number = 2, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ1, - }, - { - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = 2, - .function_number = 3, - .link_speed_capability = GEN3, - .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, - }, -}; +/* TODO: verify on hardware */ +#define phx2_mxm_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = CONFIG(ENABLE_EVAL_CARD), \ + .start_logical_lane = 0, \ + .end_logical_lane = 3, \ + .device_number = 1, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ0, \ +} + +#define phx_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = !CONFIG(DISABLE_DT_M2), \ + .start_logical_lane = 8, \ + .end_logical_lane = 11, \ + .device_number = 1, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ1, \ +} + +/* TODO: verify on hardware */ +#define phx2_ssd1_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 9, \ + .device_number = 1, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ1, \ +} + +#define gbe_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 12, \ + .end_logical_lane = 12, \ + .device_number = 1, \ + .function_number = 3, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ6, \ +} + +#define sd_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 13, \ + .end_logical_lane = 13, \ + .device_number = 2, \ + .function_number = 1, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ5, \ +} + +#define wwan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 14, \ + .end_logical_lane = CONFIG(WWAN01) ? 15 : 14, \ + .device_number = 2, \ + .function_number = 2, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ4, \ +} + +#define wlan_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 15, \ + .end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \ + .device_number = 2, \ + .function_number = 3, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ3, \ +} + +#define ssd0_dxio_descriptor { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 19, \ + .device_number = 2, \ + .function_number = 4, \ + .link_speed_capability = GEN3, \ + .turn_off_unused_lanes = true, \ + .link_aspm = ASPM_L1, \ + .link_hotplug = 0, \ + .clk_req = CLK_REQ2, \ +} static fsp_ddi_descriptor birman_ddi_descriptors[] = { { /* DDI0 - eDP */ @@ -123,8 +207,44 @@ { birman_ddi_descriptors[1].connector_type = get_ddi1_type(); - *dxio_descs = birman_dxio_descriptors; - *dxio_num = ARRAY_SIZE(birman_dxio_descriptors); + enum soc_type type = get_soc_type(); + + if (type == SOC_PHOENIX) { + printk(BIOS_DEBUG, "Using PHX DXIO\n"); + static const fsp_dxio_descriptor birman_phx_dxio_descriptors[] = { + phx_mxm_dxio_descriptor, + phx_ssd1_dxio_descriptor, + gbe_dxio_descriptor, + sd_dxio_descriptor, +#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01) + wwan_dxio_descriptor, +#endif +#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01) + wlan_dxio_descriptor, +#endif + ssd0_dxio_descriptor, + }; + *dxio_descs = birman_phx_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birman_phx_dxio_descriptors); + } else { + printk(BIOS_DEBUG, "Using PHX2 DXIO\n"); + static const fsp_dxio_descriptor birman_phx2_dxio_descriptors[] = { + phx2_mxm_dxio_descriptor, + phx2_ssd1_dxio_descriptor, + gbe_dxio_descriptor, + sd_dxio_descriptor, +#if CONFIG(WLAN0_WWAN0) || CONFIG(WWAN01) + wwan_dxio_descriptor, +#endif +#if CONFIG(WLAN0_WWAN0) || CONFIG(WLAN01) + wlan_dxio_descriptor, +#endif + ssd0_dxio_descriptor, + }; + *dxio_descs = birman_phx2_dxio_descriptors; + *dxio_num = ARRAY_SIZE(birman_phx2_dxio_descriptors); + } + *ddi_descs = birman_ddi_descriptors; *ddi_num = ARRAY_SIZE(birman_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 19 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: vendorcode/mediatek/mt8192: Fix set but unused variables
by Arthur Heymans (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Xi Chen, Xixi Chen, Yu-Ping Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74544 ) Change subject: vendorcode/mediatek/mt8192: Fix set but unused variables ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74544/comment/524b29e8_192bf16e PS5, Line 9: BUILD_TIMELESS > What's this?Means build faster? If you run 'make BUILD_TIMELESS=1' coreboot will not include timestamps. It is an easy way to check if changing code results in diffferent binaries. If they remain the same you can assume no functionality changed. -- To view, visit https://review.coreboot.org/c/coreboot/+/74544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Gerrit-Change-Number: 74544 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 12:43:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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