coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74592 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/74592/comment/15599dc3_ca0bb96c PS2, Line 10: SYS_RST_ODL > I prefer using SoC GPIO names over net names in the GPIO table for multiple reasons: […] 1. If you have the net name, the desired operation for what should happen to the GPIO becomes more apparent. 2. If the net name is different, you can update the mapping and override the init. We already do that with the GPIO_NN macros. You can see where I have done this in src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h/c 3. Same as above. if we move the net name, we'll want to initialize the GPIO in a similar/the same way. We change the GPIO mapping in baseboard/gpio.h or variant/gpio.h and verify that the init is correct. This provides a single source of truth for the GPIO allocation, makes updates to GPIO numbers all occur in a single place, and drastically improves readability. The catalyst for this change was CB:74512, but something along these lines has come up multiple times. Code review with GPIO_NN is cumbersome and lacks some meaning. Having random GPIO_NN designations throughout the code without the context of the net name is error prone and can lead to mistakes not only in selecting the correct GPIO, but in updating all of the places it's referenced in the code. -- To view, visit https://review.coreboot.org/c/coreboot/+/74592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Gerrit-Change-Number: 74592 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 21:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74478 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT ...................................................................... soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I08930ef84438140a13df74900570b126088bd1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74478 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/fsp_params.c 2 files changed, 18 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index dbe5eb1..2537013 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -100,8 +100,6 @@ int s0ix_enable; /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t tcss_d3_hot_disable; - /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t tcss_d3_cold_disable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 3c14b75..ddd49e9 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -423,7 +423,7 @@ /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; + s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08930ef84438140a13df74900570b126088bd1cb Gerrit-Change-Number: 74478 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74477 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT ...................................................................... soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74477 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 18 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b6fc43d..c466212 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -275,8 +275,6 @@ int s0ix_enable; /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t tcss_d3_hot_disable; - /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t tcss_d3_cold_disable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 704f910..7789cec 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -648,7 +648,7 @@ /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable; + s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492 Gerrit-Change-Number: 74477 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74476 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT ...................................................................... soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 19 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index cd8c480..c3a3f45 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -19,7 +19,6 @@ register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" register "SaGv" = "SaGv_Enabled" - register "TcssD3ColdDisable" = "1" # FSP Silicon # Serial I/O diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 1c280c4..0077a63 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -60,7 +60,6 @@ if (get_uint_option("thunderbolt", 1) == 0) { cfg->UsbTcPortEn = 0; cfg->TcssXhciEn = 0; - cfg->TcssD3ColdDisable = 0; tbt_pci_dev->enabled = 0; tbt_dma_dev->enabled = 0; } diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6aa0408..3de8ffa 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -148,8 +148,6 @@ /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t TcssD3HotDisable; - /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdDisable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b823f50..358536e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -327,7 +327,7 @@ if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = !config->TcssD3ColdDisable; + params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; -- To view, visit https://review.coreboot.org/c/coreboot/+/74476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Gerrit-Change-Number: 74476 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74406 ) Change subject: soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state ...................................................................... soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state Use D3COLD_SUPPORT Kconfig option to set the maximum support sleep state. Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74406 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 27 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 5067ac3..8b372ed 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -511,7 +511,10 @@ acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + if (CONFIG(D3COLD_SUPPORT)) + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + else + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); acpi_device_add_storage_d3_enable(NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/74406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d Gerrit-Change-Number: 74406 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74405 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT ...................................................................... soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 6 files changed, 38 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 17be0a2..5ad7e27 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -48,7 +48,6 @@ select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_TIGERLAKE - select SOC_INTEL_TIGERLAKE_S3 select SPI_FLASH_WINBOND select TPM_MEASURED_BOOT diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 9928591..9bca895 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -208,12 +208,6 @@ int default 6 -config SOC_INTEL_TIGERLAKE_S3 - bool - default n - help - Select if using S3 instead of S0ix to disable D3Cold - config SOC_INTEL_UART_DEV_MAX int default 3 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index be9d306..98337a3 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -676,7 +676,7 @@ } } -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -787,7 +787,7 @@ STAT = 0 } } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT /* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 3c19ef6..bbb0b6a 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -27,11 +27,11 @@ Method (_S0W, 0x0) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x04) #else Return (0x03) -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } /* @@ -40,7 +40,7 @@ */ Method (_PR0) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -52,12 +52,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } Method (_PR3) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -69,7 +69,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index fda58e7..6dbde46 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -247,16 +247,16 @@ Method (_S0W, 0x0, NotSerialized) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x4) #else Return (0x3) -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT } Method (_PR0) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } Method (_PR3) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index a3b8c8f..ddc5a66 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_S0W, 0x0, NotSerialized) { -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x4) #else Return (0x3) -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT } /* @@ -43,7 +43,7 @@ */ Name (SD3C, 0) -#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { \_SB.PCI0.D3C }) } -#endif // SOC_INTEL_TIGERLAKE_S3 +#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method -- To view, visit https://review.coreboot.org/c/coreboot/+/74405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Gerrit-Change-Number: 74405 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Jérémy Compostella (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sumeet R Pawnikar, Eric Lai. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... Patch Set 4: -Code-Review (2 comments) Patchset: PS4: We had a long call earlier today with Sumeet. I agreed to remove my -1 to let this patch move forward considering the project timeline, the fact that Sumeet seems to be having issue with values coming from the FSP and despite the fact I have concern on adding an unnecessary layer of default values duplicating Power Limits default values coming the FSP. Indeed, as Sumeet demonstrated to me this morning, the values he is adding to the `chipset.cb` are generic values from the power map (doc#640982) before tuning for a particular board design (if we exclude Fast VMode) and therefore identical to the values the FSP should be programming. So technically these values being "default" values they can indeed sit under the soc directory. Obviously, this patch can create a maintenance challenge as these settings can change in the specification and need to be updated in FSP and also in coreboot due to this patch. This is a similar situation to what we have for Alder Lake and Raptor Lake. In addition, this current infrastructure does not take into account if Fast VMode is enabled or not which is a feature impacting PL4 value. As even Power Limits can change based on board design, there is still a need for board specific customization of fine tuned Power Limits that will need to be addressed. Sumeet and I agreed that on my side, I would only work on providing the customization framework for the voltage Regulator settings when the VR/PnP team provides the settings they want. > The reason, I'm not okay with too much dependency over FSP is that the fact, FSP code and default value can change any time to address the concern from other customers which might create problem for us. First, once fine tuned, you should rely on Power Limits settings defined in the mainboard directory so changes coming the FSP shouldn't be a problem for your board designs. Second, Intel does not propagate default values changes which do not apply widely and without any very thorough validation. File src/soc/intel/meteorlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/74380/comment/a97af462_ff61529e PS4, Line 8: .tdp_pl4 = 101, In our current configuration, fast Vmode is disable which according to #640982 revision 1p1 means that PL4 should be 114W. -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 20:42:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device: Move D3COLD_SUPPORT symbol
by Lean Sheng Tan (Code Review) 20 Apr '23

20 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74404 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device: Move D3COLD_SUPPORT symbol ...................................................................... device: Move D3COLD_SUPPORT symbol Move D3COLD_SUPPORT to device, so it can be used by multiple SOCs. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74404 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 31 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index ef73c40..cdd843c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -998,6 +998,20 @@ help Provides xHCI utility functions. +config D3COLD_SUPPORT + bool + default y + help + Enable this option if all devices on your system support the + D3Cold power management state. The D3Cold state is a low-power + state where the device has been powered down and is no longer + able to maintain its context. This state can help reduce + overall system power consumption, which can be beneficial for + energy savings and thermal management. + + Please note that enabling D3Cold support may break system + suspend-to-RAM (S3) functionality. + source "src/device/dram/Kconfig" endmenu diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 9c80054..cce2052 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -332,20 +332,6 @@ int default 8 -config D3COLD_SUPPORT - bool - default y - help - Enable this option if all devices on your system support the - D3Cold power management state. The D3Cold state is a low-power - state where the device has been powered down and is no longer - able to maintain its context. This state can help reduce - overall system power consumption, which can be beneficial for - energy savings and thermal management. - - Please note that enabling D3Cold support may break system - suspend-to-RAM (S3) functionality. - config ENABLE_SATA_TEST_MODE bool "Enable test mode for SATA margining" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/74404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4 Gerrit-Change-Number: 74404 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Disable unused SPI ROM types
by Karthik Ramasubramanian (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: Martin L Roth, Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72769 ) Change subject: mb/google/skyrim: Disable unused SPI ROM types ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf Gerrit-Change-Number: 72769 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 20:30:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
by Martin L Roth (Code Review) 20 Apr '23

20 Apr '23

Attention is currently required from: John Su, Jason Nien, Jon Murphy, Jason Glenesk, Chris Wang, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74583 ) Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/skyrim/variants/markarth/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74583/comment/f812c728_c2b30f33 PS3, Line 88: if (gpio_get(EMMC_CLKREQ_GPIO)) { > Since each storage devices are behaving differently w.r. […] Great. Thank you Karthik. For now, I propose that we file a bug to update and refactor the identification for this process after we have more information. Right now, I'd like to get this merged to close the P1 issue that's causing Markarth devices with an SSD to not boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/74583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Gerrit-Change-Number: 74583 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Apr 2023 20:29:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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