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Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74593 )
Change subject: mb/google/myst: Add named GPIO's
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h:
https://review.coreboot.org/c/coreboot/+/74593/comment/b6ff0a6a_7278fa53
PS2, Line 30: #define LPC_RST_L_MB GPIO_32
This is named `LPC_RST_L` in go/myst-gpios.
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Change subject: crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> I agree. […]
The update contains only small fixes, nothing critical. Also, last weekend I have tested the toolchain (GCC and clang) with various distros, including Ubuntu 22.04, Arch Linux, Debian stable and not to forget coreboot-sdk. I'm not giving +2 to toolchain updates if I didn't test it myself. However, I am confident it's fine :)
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Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Patch Set 9:
(3 comments)
File Documentation/mainboard/hp/compaq_8200_sff.md:
https://review.coreboot.org/c/coreboot/+/74248/comment/568632da_666539b3
PS9, Line 81: need fix
need *to* fix
https://review.coreboot.org/c/coreboot/+/74248/comment/90fadc6a_f4937d35
PS9, Line 86: filesystem
You can drop "filesystem" as CBFS stands for "coreboot filesystem"
https://review.coreboot.org/c/coreboot/+/74248/comment/5ddaeaa2_e032dbce
PS9, Line 89: descrtiptor
spelling: descriptor
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Change subject: Documentation/mainboard: Add missing Asus toctree references
......................................................................
Patch Set 1: Code-Review+2
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Hello Felix Singer, build bot (Jenkins), Nicholas Chin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Documentation/mainboard/hp: Add more about internal flashing
Add a more detailed explanation of internal flashing
on the HP Compaq 8200 Elite SFF.
Signed-off-by: Václav Straka <venda.straka(a)gmail.com>
Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636
---
M Documentation/mainboard/hp/compaq_8200_sff.md
A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg
2 files changed, 102 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/9
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Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Patch Set 8:
(1 comment)
File Documentation/mainboard/hp/compaq_8200_sff.md:
https://review.coreboot.org/c/coreboot/+/74248/comment/f1d998f3_4f96b823
PS5, Line 80: The temporary flash size to set in coreboot is 2 MB, and you can fill
> It would be good to mention the CBFS size that should be used as well, just for clarity. […]
Done
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Hello Felix Singer, build bot (Jenkins), Nicholas Chin,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Documentation/mainboard/hp: Add more about internal flashing
Add a more detailed explanation of internal flashing
on the HP Compaq 8200 Elite SFF.
Signed-off-by: Václav Straka <venda.straka(a)gmail.com>
Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636
---
M Documentation/mainboard/hp/compaq_8200_sff.md
A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg
2 files changed, 102 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/8
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73889 )
Change subject: soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
......................................................................
soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
srcclk_pin is 0-based and '0' is a valid clock source number. If
srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.
BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI entries are generated as
expected. For those PCI devices with RTD3 driver whose srcclk_pin to
0, the RTD3 entries should not be missing due to check error.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 27 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Bora Guvendik: Looks good to me, approved
Jérémy Compostella: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 8b372ed..82336d9 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -419,9 +419,10 @@
return;
}
}
- if (config->srcclk_pin == 0) {
+ if (config->srcclk_pin == -1) {
if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) {
- printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__);
+ printk(BIOS_ERR, "%s: Can not export SRCK method since clock source gating is not enabled\n",
+ __func__);
return;
}
}
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