coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/rex: Enable asynchronous End-Of-Post
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74562 ) Change subject: mb/google/rex: Enable asynchronous End-Of-Post ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74562/comment/f91245fa_69a61696 PS1, Line 92: if !BOARD_GOOGLE_REX_COMMON would it be possible to use "if !SOC_INTEL_CSE_SEND_EOP_ASYNC" instead to avoid using board-specific kconfig options in the soc code? feel free to just ack this and look into that later -- To view, visit https://review.coreboot.org/c/coreboot/+/74562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Gerrit-Change-Number: 74562 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 22:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Send CSE EOP Async CMD early
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74561 ) Change subject: soc/intel/meteorlake: Send CSE EOP Async CMD early ...................................................................... soc/intel/meteorlake: Send CSE EOP Async CMD early This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample which causes idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of boot time savings (across warm and cold reset scenarios) Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/chip.c 1 file changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 60f85ba..1f7eab81 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -7,6 +7,7 @@ #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> +#include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/p2sb.h> @@ -151,6 +152,22 @@ /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pcie_rp_table()); + + /* + * Earlier when coreboot used to send EOP at late as possible caused + * issue of delayed response from CSE since CSE was busy loading payload. + * To resolve the issue, EOP should be sent earlier than current sequence + * in the boot sequence at BS_DEV_INIT. + * + * Intel CSE team recommends to send EOP close to FW init (between FSP-S + * exit and current boot sequence) to reduce message response time from + * CSE hence moving sending EOP to earlier stage. + */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { + printk(BIOS_INFO, "Sending EOP early from SoC\n"); + cse_send_end_of_post(); + } } static void cpu_fill_ssdt(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/74561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a Gerrit-Change-Number: 74561 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 40: Code-Review+1 (2 comments) Patchset: PS40: haven't checked the reset lines, but the rest looks good to me File src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/74112/comment/5d34a744_d927dfcf PS38, Line 11: PCIE_GPP_2_0_DEVFN > Done that patch has landed, so now everything should be correct -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 40 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 22:02:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74110 ) ( 32 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Add eSPI configuration ...................................................................... mb/google/myst: Add eSPI configuration Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/bootblock.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 5 files changed, 97 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 24caa52..8739506 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -19,6 +19,7 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select MAINBOARD_HAS_CHROMEOS + select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PHOENIX config DEVICETREE diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c index 0877807..4d4d7e7 100644 --- a/src/mainboard/google/myst/bootblock.c +++ b/src/mainboard/google/myst/bootblock.c @@ -1,7 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/espi.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <soc/espi.h> + +void mb_set_up_early_espi(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + variant_espi_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); + + espi_switch_to_spi1_pads(); +} void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index fbc9e93..466b2dc 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,5 +1,43 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/phoenix + + # eSPI Configuration + # TODO(b/276913952) bump clock back up to 33MHz once things seem to be working well. + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + .size = 1, + }, + .generic_io_range[1] = { + .base = 0x66, + .size = 1, + }, + .generic_io_range[2] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[3] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[4] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), + }" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 0add7a0..b2eccff 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -173,6 +173,23 @@ /* TODO(b/275965982): Fill bootblock gpio configuration */ }; +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI1_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), +}; + void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(base_gpio_table); @@ -185,6 +202,12 @@ *gpio = bootblock_gpio_table; } +void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + *gpio = espi_gpio_table; +} + __weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = 0; diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 3f69548..a39d2bf 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,9 @@ /* This function provides GPIO init in bootblock. */ void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + /* * This function allows variant to override any GPIOs that are different than the base GPIO * configuration provided by baseboard_gpio_table(). -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 34 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Karthik Ramasubramanian (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74592 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/74592/comment/ab6c3a99_93fe6af7 PS2, Line 10: SYS_RST_ODL > 3. Same as above. if we move the net name, we'll want to initialize the GPIO in a similar/the same way. We change the GPIO mapping in baseboard/gpio.h or variant/gpio.h and verify that the init is correct. This provides a single source of truth for the GPIO allocation, makes updates to GPIO numbers all occur in a single place, and drastically improves readability. We moved netnames between build phases themselves - eg. GSC_SOC_INT moved from GPIO_X to GPIO_Y within guybrush phase1 and pahse2 itself. Not between guybrush and nipperkin. So phase specific overrides will have GPIO_NN still. > Code review with GPIO_NN is cumbersome and lacks some meaning. Having random GPIO_NN designations throughout the code without the context of the net name We are not configuring the GPIOs in random places in the code. They are all done in the GPIO table with comments above indicating their purpose. Using GPIO_NN is prone to bugs when configuring the hardware blocks themselves. Net names definitely come in handy there. So I prefer to limit the use-case there before introducing another set of macros to configure the GPIOs themselves. -- To view, visit https://review.coreboot.org/c/coreboot/+/74592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Gerrit-Change-Number: 74592 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 21:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Documentation/mainboard: Add missing Asus toctree references
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Singer, Angel Pons, Nicholas Chin. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74189 ) Change subject: Documentation/mainboard: Add missing Asus toctree references ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7883d48bfbe6bff5595aa9303f9d6f4a55eadc9c Gerrit-Change-Number: 74189 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 21:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74565 ) Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR ...................................................................... soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR Parts of this file were still a copy of the file from the Mendocino SoC, so update the file to match the PPR #57019 Rev 3.03 and the chipset devicetree of the Phoenix SoC. Phoenix has 4 GFX/GPP PCIe bridges/ports, the numbering scheme of the GPP PCIe bridges/ports was changed so that the numbers match the device and function numbers, and there are new device functions for the IPU and the USB4 controller and router devices. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74565 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/include/soc/pci_devs.h 1 file changed, 67 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/include/soc/pci_devs.h b/src/soc/amd/phoenix/include/soc/pci_devs.h index efe84bc..0dde0ba 100644 --- a/src/soc/amd/phoenix/include/soc/pci_devs.h +++ b/src/soc/amd/phoenix/include/soc/pci_devs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #ifndef AMD_PHOENIX_PCI_DEVS_H #define AMD_PHOENIX_PCI_DEVS_H @@ -20,36 +18,52 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* PCIe GFX/GPP Bridge device 1 with no ports */ +/* PCIe GFX/GPP Bridge device 1 with 4 ports */ #define PCIE_GPP_BRIDGE_1_DEV 0x1 +#define PCIE_GPP_1_1_FUNC 1 +#define PCIE_GPP_1_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) +#define SOC_GPP_1_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) + +#define PCIE_GPP_1_2_FUNC 2 +#define PCIE_GPP_1_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) +#define SOC_GPP_1_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) + +#define PCIE_GPP_1_3_FUNC 3 +#define PCIE_GPP_1_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) +#define SOC_GPP_1_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_3_FUNC) + +#define PCIE_GPP_1_4_FUNC 4 +#define PCIE_GPP_1_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_4_FUNC) +#define SOC_GPP_1_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_4_FUNC) + /* PCIe GPP Bridge device 2 with up to 6 ports */ #define PCIE_GPP_BRIDGE_2_DEV 0x2 -#define PCIE_GPP_2_0_FUNC 1 -#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) -#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) - -#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_FUNC 1 #define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) #define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) -#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_FUNC 2 #define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) #define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) -#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_FUNC 3 #define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) #define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) -#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_FUNC 4 #define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) #define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) -#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_FUNC 5 #define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) #define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define PCIE_GPP_2_6_FUNC 6 +#define PCIE_GPP_2_6_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) +#define SOC_GPP_2_6_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) + /* PCIe Bridges to Bus A, Bus B and Bus C devices */ #define PCIE_ABC_BRIDGE_DEV 0x8 @@ -85,13 +99,29 @@ #define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define GFX_IPU_DEV 0x0 +#define GFX_IPU_FUNC 1 +#define GFX_IPU_DEVFN PCI_DEVFN(GFX_IPU_DEV, GFX_IPU_FUNC) + #define PCIE_ABC_C_FUNC 3 #define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) -#define XHCI2_DEV 0x0 -#define XHCI2_FUNC 0 -#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC) +#define USB4_XHCI0_DEV 0x0 +#define USB4_XHCI0_FUNC 3 +#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC) + +#define USB4_XHCI1_DEV 0x0 +#define USB4_XHCI1_FUNC 4 +#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC) + +#define USB4_ROUTER0_DEV 0x0 +#define USB4_ROUTER0_FUNC 5 +#define USB4_ROUTER0_DEVFN PCI_DEVFN(USB4_ROUTER0_DEV, USB4_ROUTER0_FUNC) + +#define USB4_ROUTER1_DEV 0x0 +#define USB4_ROUTER1_FUNC 6 +#define USB4_ROUTER1_DEVFN PCI_DEVFN(USB4_ROUTER1_DEV, USB4_ROUTER1_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 -- To view, visit https://review.coreboot.org/c/coreboot/+/74565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9429c03839bb0199a04cd6cafe9a955ebdacc91 Gerrit-Change-Number: 74565 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/devicetree: drop i2s_ac97 device
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74564 ) Change subject: soc/amd/phoenix/devicetree: drop i2s_ac97 device ...................................................................... soc/amd/phoenix/devicetree: drop i2s_ac97 device In both PPR #57019 Rev 3.03 and PPR #57396 Rev 3.04, the i2s_ac97 function on bus C isn't mentioned any more and the microarchitecture specification document for this SoC also doesn't mention it, so remove it from the devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74564 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 2d92f14..055e125 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -91,7 +91,6 @@ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable - device pci 0.2 alias i2s_ac97 off end device pci 0.3 alias usb4_xhci_0 off chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" -- To view, visit https://review.coreboot.org/c/coreboot/+/74564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd115953bdd60e1dfcc79797b0c2158e5d861636 Gerrit-Change-Number: 74564 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74567 ) Change subject: soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg ...................................................................... soc/amd/stoneyridge/northbridge: fix indentation in set_mmio_addr_reg Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b1d2bdd..068ba56 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -50,9 +50,9 @@ /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(SOC_ADDR_DEV, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/74567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e067f6fb2bab66d9b2f6965636845dfd8b7cacd Gerrit-Change-Number: 74567 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Don't offer D3Cold when it's disabled
by Michael Niewöhner (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Singer, Sean Rhodes, Nico Huber, Tarun Tuli, Subrata Banik, Kapil Porwal. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74479 ) Change subject: soc/intel/meteorlake: Don't offer D3Cold when it's disabled ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996 Gerrit-Change-Number: 74479 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 20 Apr 2023 21:05:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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