coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74613 ) Change subject: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb ...................................................................... soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74613 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 21 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index ccfa9cb..bafeabb 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -327,8 +327,8 @@ uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); uint32_t mem_useable = (uintptr_t)cbmem_top(); - msr_t tom = rdmsr(TOP_MEM); - msr_t high_tom = rdmsr(TOP_MEM2); + uint32_t tom = get_top_of_mem_below_4gb(); + uint64_t high_tom = get_top_of_mem_above_4g(); uint64_t high_mem_useable; int idx = 0x10; @@ -352,16 +352,15 @@ /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource_kb(dev, idx++, mem_useable / KiB, - (tom.lo - mem_useable) / KiB); + (tom - mem_useable) / KiB); /* If there is memory above 4GiB */ - if (high_tom.hi) { + if (high_tom >> 32) { /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else - high_mem_useable = ((uint64_t)high_tom.lo | - ((uint64_t)high_tom.hi << 32)); + high_mem_useable = high_tom; ram_resource_kb(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); -- To view, visit https://review.coreboot.org/c/coreboot/+/74613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Gerrit-Change-Number: 74613 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74612 ) Change subject: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb ...................................................................... soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74612 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/acpi/tables.c 1 file changed, 19 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index b7c942c..17db421 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -40,7 +40,6 @@ /* Used by \_SB.PCI0._CRS */ void acpi_fill_root_complex_tom(const struct device *device) { - msr_t msr; const char *scope; assert(device); @@ -49,9 +48,8 @@ assert(scope); acpigen_write_scope(scope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + /* * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. @@ -60,6 +58,6 @@ * Shift value right by 20 bit to make it fit into 32bit, * giving us 1MB granularity and a limit of almost 4Exabyte of memory. */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4g() >> 20); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Gerrit-Change-Number: 74612 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Matt DeVillier, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74614 ) Change subject: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Gerrit-Change-Number: 74614 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:13:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Matt DeVillier, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74613 ) Change subject: soc/amd/stoneyridge/northbridge: use get_top_of_mem_[below,above]_4gb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04f2a3744aee9beedaa97b154a652ce6f0c705c0 Gerrit-Change-Number: 74613 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:12:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Drop unused include <version.h>
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74448 ) Change subject: Drop unused include <version.h> ...................................................................... Drop unused include <version.h> Change-Id: I7d0718b5d2e0dd16eb90f63dd9d33329a2d808ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74448 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/lib/hardwaremain.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c 8 files changed, 14 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 714452d..47022ac 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -23,7 +23,6 @@ #include <timer.h> #include <timestamp.h> #include <types.h> -#include <version.h> static boot_state_t bs_pre_device(void *arg); static boot_state_t bs_dev_init_chips(void *arg); diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1a824a7..341d9e0 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -23,7 +23,6 @@ #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <version.h> #include "chip.h" unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d6dec6f..39f13b6 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -22,7 +22,6 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/northbridge.h> -#include <version.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index fe286fe..1865d36 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <acpi/acpi.h> #include <device/device.h> -#include <version.h> #include "hudson.h" #include "smi.h" diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 681d09c..d83925d 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -7,7 +7,6 @@ #include <acpi/acpi.h> #include <device/device.h> #include <device/pci.h> -#include <version.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 6d63e72..3f97145 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <version.h> #include <southbridge/intel/common/pmbase.h> #include "i82801gx.h" #include "chip.h" diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 54ebcbd..78443ea 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <version.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 9d60ca5a..f0f4ca1 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -3,7 +3,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <version.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) -- To view, visit https://review.coreboot.org/c/coreboot/+/74448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d0718b5d2e0dd16eb90f63dd9d33329a2d808ba Gerrit-Change-Number: 74448 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/braswell: Replace <build.h> with <version.h>
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74447 ) Change subject: soc/intel/braswell: Replace <build.h> with <version.h> ...................................................................... soc/intel/braswell: Replace <build.h> with <version.h> To use generated build.h one should have had a pre-requisite in the Makefile. Reference coreboot_build_date from lib/version.c instead. Change-Id: Icd6fa2ddf8aa584b0f51ba130592f227bbdad975 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74447 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/braswell/bootblock/bootblock.c 1 file changed, 21 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 2c9783a..8ab95ef 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -2,7 +2,6 @@ #include <arch/io.h> #include <bootblock_common.h> -#include <build.h> #include <console/console.h> #include <device/pci_ops.h> #include <fsp/util.h> @@ -14,6 +13,7 @@ #include <soc/msr.h> #include <soc/pm.h> #include <soc/spi.h> +#include <version.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -79,11 +79,10 @@ { int rtc_failed = rtc_failure(); - if (rtc_failed) { + if (rtc_failed) printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n", - COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20, - COREBOOT_BUILD_YEAR_BCD); - } + coreboot_build_date.month, coreboot_build_date.day, + coreboot_build_date.century, coreboot_build_date.year); cmos_init(rtc_failed); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd6fa2ddf8aa584b0f51ba130592f227bbdad975 Gerrit-Change-Number: 74447 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/ipmi: Replace <build.h> with <version.h>
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74446 ) Change subject: drivers/ipmi: Replace <build.h> with <version.h> ...................................................................... drivers/ipmi: Replace <build.h> with <version.h> To use generated build.h one should have had a pre-requisite in the Makefile. Reference coreboot_version from lib/version.c instead. Change-Id: I7f10acabf1838deb90fde8215a32718028096852 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74446 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/ipmi/supermicro_oem.c 1 file changed, 22 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index c63da5f..fcf97f4 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -5,7 +5,7 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_if.h> #include <string.h> -#include <build.h> +#include <version.h> #include "ipmi_supermicro_oem.h" #define IPMI_NETFN_OEM 0x30 @@ -20,7 +20,6 @@ static void set_coreboot_ver(const uint16_t kcs_port) { - const char *coreboot_ver = COREBOOT_VERSION; struct ipmi_oem_set_bios_str bios_ver; struct ipmi_rsp rsp; int ret; @@ -28,9 +27,9 @@ /* Only 8 characters are visible in UI. Cut of on first dash */ for (i = 0; i < 15; i++) { - if (coreboot_ver[i] == '-') + if (coreboot_version[i] == '-') break; - bios_ver.str[i] = coreboot_ver[i]; + bios_ver.str[i] = coreboot_version[i]; } bios_ver.str[i] = 0; bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; @@ -50,7 +49,7 @@ struct ipmi_rsp rsp; int ret; - strncpy(bios_ver.str, COREBOOT_DMI_DATE, 15); + strncpy(bios_ver.str, coreboot_dmi_date, 15); bios_ver.str[15] = 0; bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; -- To view, visit https://review.coreboot.org/c/coreboot/+/74446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f10acabf1838deb90fde8215a32718028096852 Gerrit-Change-Number: 74446 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74612 ) Change subject: soc/amd/common/block/acpi/tables: use get_top_of_mem_[below,above]_4gb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35895340f6e747e2f5e1669d40f40b201d8c1845 Gerrit-Change-Number: 74612 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:12:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74611 ) Change subject: nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb ...................................................................... nb/amd/pi/00730F01/northbridge: use get_top_of_mem_[below,above]_4gb Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 19 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d963171..d373493 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -538,13 +538,11 @@ static void northbridge_fill_ssdt_generator(const struct device *device) { - msr_t msr; char pscope[] = "\\_SB.PCI0"; acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + /* * Since XP only implements parts of ACPI 2.0, we can't use a qword * here. @@ -553,7 +551,7 @@ * Shift value right by 20 bit to make it fit into 32bit, * giving us 1MB granularity and a limit of almost 4Exabyte of memory. */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4g() >> 20); acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd Gerrit-Change-Number: 74611 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74610 ) Change subject: include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb ...................................................................... include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb The top of memory below 4GB will always fit into 32 bits, so change the return type accordingly. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74610 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/include/cpu/amd/mtrr.h 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index b8b820c..e96dc90 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -65,7 +65,7 @@ ); } -static inline uint64_t get_top_of_mem_below_4gb(void) +static inline uint32_t get_top_of_mem_below_4gb(void) { return rdmsr(TOP_MEM).lo; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b463a17f2db3b7a99ff3572f318c9c22aac7431 Gerrit-Change-Number: 74610 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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