coreboot-gerrit April 2023

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[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... Patch Set 1: -Code-Review (1 comment) File src/cpu/amd/pi/00730F01/fixme.c: https://review.coreboot.org/c/coreboot/+/74616/comment/e71c9630_4b15f9db PS1, Line 19: 0x00fedf00 Should this be changed to 0xfedf0000 for our functions? It looks like it gets fixed in the next patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:24:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add VPU into the DMAR SATC table
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74221 ) Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table ...................................................................... soc/intel/meteorlake: Add VPU into the DMAR SATC table This change adds the VPU into the DMAR SATC table in order to support the VPU IO virtualization. BUG=None TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table includeded the VPU entry. Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Signed-off-by: John Zhao <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74221 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/acpi.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index c679af3..c6e7cab 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -270,6 +270,8 @@ current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0); + if (is_devfn_enabled(PCI_DEVFN_VPU)) + current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_VPU, 0); acpi_dmar_satc_fixup(tmp, current); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/74221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Gerrit-Change-Number: 74221 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74582 ) Change subject: soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function ...................................................................... soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/meteorlake/romstage/romstage.c 3 files changed, 33 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Kangheui Won: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index a3273e6..740a4a2 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -180,11 +180,8 @@ if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1e2a052..14a7381 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1077,7 +1077,7 @@ return handle_cse_sub_part_fw_update_rv(rv); } -void cse_fw_sync(void) +static void do_cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; @@ -1152,6 +1152,13 @@ } } +void cse_fw_sync(void) +{ + timestamp_add_now(TS_CSE_FW_SYNC_START); + do_cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); +} + static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1214,11 +1221,8 @@ if (acpi_get_sleep_type() == ACPI_S3) return; - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL); diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index ebb440c..b5351de 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -128,11 +128,8 @@ /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) -- To view, visit https://review.coreboot.org/c/coreboot/+/74582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Gerrit-Change-Number: 74582 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Refactor ramstage cse fw sync() function
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74581 ) Change subject: soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() function ...................................................................... soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() function This patch refactors sleep type check inside ramstage_cse_fw_sync() to avoid additional logic while performing cse_fw_sync() operation. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74581 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 23 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Kangheui Won: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4cc9e19..1e2a052 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1211,10 +1211,10 @@ static void ramstage_cse_fw_sync(void *unused) { - bool s3wake; - s3wake = acpi_get_sleep_type() == ACPI_S3; + if (acpi_get_sleep_type() == ACPI_S3) + return; - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) { timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); -- To view, visit https://review.coreboot.org/c/coreboot/+/74581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Gerrit-Change-Number: 74581 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor) Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 revision 001 (DOC# 634545) Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 699 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index bf4156c..0a9fe18 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1114,6 +1114,7 @@ case PCI_DEVICE_ID_INTEL_ADL_P: case PCI_DEVICE_ID_INTEL_ADL_M: case PCI_DEVICE_ID_INTEL_RPL_P: + case PCI_DEVICE_ID_INTEL_JSL: case PCI_DEVICE_ID_INTEL_EHL: case PCI_DEVICE_ID_INTEL_EBG: print_gpio_groups(sb); diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index fd5be73..7afe682 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -23,6 +23,7 @@ #include "gpio_names/alderlake_h.h" #include "gpio_names/alderlake_p.h" #include "gpio_names/elkhartlake.h" +#include "gpio_names/jasperlake.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) @@ -232,6 +233,10 @@ *community_count = ARRAY_SIZE(alderlake_pch_p_communities); *pad_stepping = 16; return alderlake_pch_p_communities; + case PCI_DEVICE_ID_INTEL_JSL: + *community_count = ARRAY_SIZE(jasperlake_pch_communities); + *pad_stepping = 16; + return jasperlake_pch_communities; case PCI_DEVICE_ID_INTEL_EHL: *community_count = ARRAY_SIZE(elkhartlake_pch_communities); *pad_stepping = 16; diff --git a/util/inteltool/gpio_names/jasperlake.h b/util/inteltool/gpio_names/jasperlake.h new file mode 100644 index 0000000..f6c1dc6 --- /dev/null +++ b/util/inteltool/gpio_names/jasperlake.h @@ -0,0 +1,673 @@ +#ifndef GPIO_NAMES_JASPERLAKE +#define GPIO_NAMES_JASPERLAKE + +#include "gpio_groups.h" + +/* ----------------------------- Jasper Lake ----------------------------- */ + +const char *const jasperlake_pch_group_a_names[] = { + "GPP_A00", "ESPI_IO_0", "n/a", + "GPP_A01", "ESPI_IO_1", "n/a", + "GPP_A02", "ESPI_IO_2", "n/a", + "GPP_A03", "ESPI_IO_3", "n/a", + "GPP_A04", "ESPI_CS_N", "n/a", + "GPP_A05", "ESPI_CLK", "n/a", + "GPP_A06", "ESPI_RESET_N", "n/a", + "GPP_A07", "SMB_CLK", "n/a", + "GPP_A08", "SMB_DATA", "n/a", + "GPP_A09", "SMB_ALERT_N", "n/a", + "GPP_A10", "CPU_GP_0", "n/a", + "GPP_A11", "CPU_GP_1", "n/a", + "GPP_A12", "USB_OC1_N", "n/a", + "GPP_A13", "USB_OC2_N", "n/a", + "GPP_A14", "USB_OC3_N", "n/a", + "GPP_A15", "n/a", "n/a", + "GPP_A16", "DDI1_HPD", "TIME_SYNC_1", + "GPP_A17", "DDI0_HPD", "n/a", + "GPP_A18", "USB_OC0_N", "n/a", + "GPP_A19", "PCHHOT_N", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_a_names) / 3, + .func_count = 3, + .pad_names = jasperlake_pch_group_a_names, +}; + +const char *const jasperlake_pch_group_b_names[] = { + "GPP_B00", "PMC_CORE_VID0", "n/a", "n/a", + "GPP_B01", "PMC_CORE_VID1", "n/a", "n/a", + "GPP_B02", "PMC_VRALERT_N", "n/a", "n/a", + "GPP_B03", "CPU_GP_2", "n/a", "n/a", + "GPP_B04", "CPU_GP_3", "n/a", "n/a", + "GPP_B05", "PCIE_CLKREQ0_N", "n/a", "n/a", + "GPP_B06", "PCIE_CLKREQ1_N", "n/a", "n/a", + "GPP_B07", "PCIE_CLKREQ2_N", "n/a", "n/a", + "GPP_B08", "PCIE_CLKREQ3_N", "n/a", "n/a", + "GPP_B09", "PCIE_CLKREQ4_N", "n/a", "n/a", + "GPP_B10", "PCIE_CLKREQ5_N", "n/a", "n/a", + "GPP_B11", "PMCALERT_N", "n/a", "n/a", + "GPP_B12", "PMC_SLP_S0_N", "n/a", "n/a", + "GPP_B13", "PMC_PLTRST_N", "n/a", "n/a", + "GPP_B14", "SPKR", "GSPI0_CS1_N", "n/a", + "GPP_B15", "GSPI0_CS0_N", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "UART2A_RXD", "n/a", + "GPP_B18", "GSPI0_MOSI", "UART2A_TXD", "n/a", + "GPP_B19", "GSPI1_CS0_N", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "NFC_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "NFC_CLKREQ", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "DDI2_HPD", "TIME_SYNC_0", "GSPI1_CS1_N", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_b_names) / 4, + .func_count = 4, + .pad_names = jasperlake_pch_group_b_names, +}; + +const char *const jasperlake_pch_group_c_names[] = { + "GPP_C00", "n/a", "n/a", "n/a", + "GPP_C01", "n/a", "n/a", "n/a", + "GPP_C02", "n/a", "n/a", "n/a", + "GPP_C03", "n/a", "n/a", "n/a", + "GPP_C04", "n/a", "n/a", "n/a", + "GPP_C05", "n/a", "n/a", "n/a", + "GPP_C06", "n/a", "PMC_SUSWARN_N_PMC_SUSPWRDNACK", "n/a", + "GPP_C07", "n/a", "PMC_SUSACK_N", "n/a", + "GPP_C08", "UART0_RXD", "n/a", "n/a", + "GPP_C09", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS_N", "n/a", "n/a", + "GPP_C11", "UART0_CTS_N", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "n/a", "n/a", + "GPP_C13", "UART1_TXD", "n/a", "n/a", + "GPP_C14", "UART1_RTS_N", "n/a", "n/a", + "GPP_C15", "UART1_CTS_N", "n/a", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "CNV_MFUART0_RXD", + "GPP_C21", "UART2_TXD", "n/a", "CNV_MFUART0_TXD", + "GPP_C22", "UART2_RTS_N", "n/a", "CNV_MFUART0_RTS_N", + "GPP_C23", "UART2_CTS_N", "n/a", "CNV_MFUART0_CTS_N", +}; + +const struct gpio_group jasperlake_pch_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_c_names) / 4, + .func_count = 4, + .pad_names = jasperlake_pch_group_c_names, +}; + +const char *const jasperlake_pch_group_d_names[] = { + "GPP_D00", "n/a", "BK_0", "SBK_0", "n/a", + "GPP_D01", "n/a", "BK_1", "SBK_1", "n/a", + "GPP_D02", "n/a", "BK_2", "SBK_2", "n/a", + "GPP_D03", "n/a", "BK_3", "SBK_3", "n/a", + "GPP_D04", "n/a", "n/a", "n/a", "n/a", + "GPP_D05", "n/a", "n/a", "n/a", "n/a", + "GPP_D06", "n/a", "n/a", "n/a", "n/a", + "GPP_D07", "n/a", "n/a", "n/a", "n/a", + "GPP_D08", "n/a", "GSPI2_SPI2_CS0_N", "UART0A_RXD", "n/a", + "GPP_D09", "n/a", "GSPI2_CLK", "UART0A_TXD", "n/a", + "GPP_D10", "n/a", "GSPI2_MISO", "UART0A_RTS_N", "n/a", + "GPP_D11", "n/a", "GSPI2_MOSI", "UART0A_CTS_N", "n/a", + "GPP_D12", "n/a", "n/a", "I2C4B_SDA", "n/a", + "GPP_D13", "n/a", "n/a", "I2C4B_SCL", "n/a", + "GPP_D14", "n/a", "GSPI2_CS1_N", "n/a", "n/a", + "GPP_D15", "n/a", "n/a", "n/a", "CNV_WCEN", + "GPP_D16", "n/a", "n/a", "n/a", "n/a", + "GPP_D17", "n/a", "n/a", "n/a", "n/a", + "GPP_D18", "AVS_I2S_MCLK", "n/a", "n/a", "n/a", + "GPP_D19", "CNV_MFUART2_RXD", "n/a", "n/a", "n/a", + "GPP_D20", "CNV_MFUART2_TXD", "n/a", "n/a", "n/a", + "GPP_D21", "CNV_PA_BLANKING", "n/a", "n/a", "n/a", + "GPP_D22", "I2C5_SDA", "n/a", "n/a", "n/a", + "GPP_D23", "I2C5_SCL", "n/a", "n/a", "n/a", + "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", "n/a", "n/a", "n/a", + "SPI1_CLK_LOOPBK", "SPI1_CLK_LOOPBK", "n/a", "n/a", "n/a", + +}; + +const struct gpio_group jasperlake_pch_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_d_names) / 5, + .func_count = 5, + .pad_names = jasperlake_pch_group_d_names, +}; + + +const char *const jasperlake_pch_hvcmos_names[] = { + "L_BKLTEN", "L_BKLTEN", + "L_BKLTCTL", "L_BKLTCTL", + "LVDDEN", "LVDDEN", + "SYS_PWROK", "SYS_PWROK", + "SYS_RESETB", "SYS_RESETB", + "MLK_RSTB", "MLK_RSTB", +}; + +const struct gpio_group jasperlake_pch_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_hvcmos_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_hvcmos_names, + }; + +const char *const jasperlake_pch_group_e_names[] = { + "GPP_E00", "n/a", "IMGCLKOUT_0", "n/a", "n/a", "n/a", "n/a", + "GPP_E01", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E02", "IMGCLKOUT_1", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E03", "n/a", "SATA_0_DEVSLP", "n/a", "n/a", "n/a", "n/a", + "GPP_E04", "IMGCLKOUT_2", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E05", "SATA_LED_N", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E06", "IMGCLKOUT_3", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E07", "n/a", "SATA_1_DEVSLP", "n/a", "n/a", "n/a", "n/a", + "GPP_E08", "n/a", "Reserved", "n/a", "n/a", "SATA_0_GP", "n/a", + "GPP_E09", "n/a", "SML_CLK0", "n/a", "n/a", "SATA_1_GP", "n/a", + "GPP_E10", "n/a", "SML_DATA0", "n/a", "n/a", "n/a", "n/a", + "GPP_E11", "n/a", "n/a", "n/a", "n/a", "n/a", "BSSB_LS3_RX", + "GPP_E12", "IMGCLKOUT_4", "n/a", "n/a", "n/a", "n/a", "BSSB_LS3_TX", + "GPP_E13", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "BSSB_LS0_RX", "n/a", + "GPP_E14", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "BSSB_LS0_TX", "n/a", + "GPP_E15", "DDI1_DDC_SCL", "n/a", "n/a", "n/a", "BSSB_LS1_RX", "n/a", + "GPP_E16", "DDI1_DDC_SDA", "n/a", "n/a", "n/a", "BSSB_LS1_TX", "n/a", + "GPP_E17", "DDI2_DDC_SCL", "n/a", "n/a", "n/a", "BSSB_LS2_RX", "n/a", + "GPP_E18", "DDI2_DDC_SDA", "n/a", "n/a", "n/a", "BSSB_LS2_TX", "n/a", + "GPP_E19", "IMGCLKOUT_5", "Reserved", "n/a", "PCIE_LNK_DOWN", "n/a", "n/a", + "GPP_E20", "CNV_BRI_DT", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E21", "CNV_BRI_RSP", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E22", "CNV_RGI_DT", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_E23", "CNV_RGI_RSP", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_e_names) / 7, + .func_count = 7, + .pad_names = jasperlake_pch_group_e_names, +}; + +const char *const jasperlake_pch_jtag_names[] = { + "JTAG_TD0", "JTAG_TD0", + "JTAGX", "JTAGX", + "PRDYB", "PRDYB", + "PREQB", "PREQB", + "CPU_TRSTB", "CPU_TRSTB", + "JTAG_TDI", "JTAG_TDI", + "JTAG_TMS", "JTAG_TMS", + "JTAG_TCK", "JTAG_TCK", + "ITP_PMODE", "ITP_PMODE", +}; + +const struct gpio_group jasperlake_pch_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_jtag_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_jtag_names, +}; + +const char *const jasperlake_pch_group_f_names[] = { + "GPP_F00", "n/a", + "GPP_F01", "n/a", + "GPP_F02", "n/a", + "GPP_F03", "n/a", + "GPP_F04", "CNV_RF_RESET_N", + "GPP_F05", "n/a", + "GPP_F06", "n/a", + "GPP_F07", "EMMC_CMD", + "GPP_F08", "EMMC_DATA0", + "GPP_F09", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESET_N", + "GPP_F19", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_f_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_f_names, +}; + +const char *const jasperlake_pch_group_g_names[] = { + "GPP_G00", "SD_SDIO_CMD", + "GPP_G01", "SD_SDIO_D0", + "GPP_G02", "SD_SDIO_D1", + "GPP_G03", "SD_SDIO_D2", + "GPP_G04", "SD_SDIO_D3", + "GPP_G05", "SD_SDIO_CD_N", + "GPP_G06", "SD_SDIO_CLK", + "GPP_G07", "SD_SDIO_WP", +}; + +const struct gpio_group jasperlake_pch_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_g_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_g_names, +}; + +const char *const jasperlake_pch_group_h_names[] = { + "GPP_H00", "n/a", "n/a", "n/a", + "GPP_H01", "SD_SDIO_PWR_EN_N", "n/a", "CNV_RF_RESET_N", + "GPP_H02", "n/a", "n/a", "MODEM_CLKREQ", + "GPP_H03", "SX_EXIT_HOLDOFF_N", "n/a", "n/a", + "GPP_H04", "I2C2_SDA", "n/a", "n/a", + "GPP_H05", "I2C2_SCL", "n/a", "n/a", + "GPP_H06", "I2C3_SDA", "n/a", "n/a", + "GPP_H07", "I2C3_SCL", "n/a", "n/a", + "GPP_H08", "I2C4_SDA", "n/a", "n/a", + "GPP_H09", "I2C4_SCL", "n/a", "n/a", + "GPP_H10", "CPU_C10_GATE_N", "n/a", "n/a", + "GPP_H11", "AVS_I2S2_SCLK", "n/a", "n/a", + "GPP_H12", "AVS_I2S2_SFRM", "CNV_RF_RESET_N", "n/a", + "GPP_H13", "AVS_I2S2_TXD", "MODEM_CLKREQ", "n/a", + "GPP_H14", "AVS_I2S2_RXD", "n/a", "n/a", + "GPP_H15", "AVS_I2S1_SCLK", "n/a", "n/a", + "GPP_H16", "n/a", "n/a", "n/a", + "GPP_H17", "n/a", "n/a", "n/a", + "GPP_H18", "n/a", "n/a", "n/a", + "GPP_H19", "n/a", "n/a", "n/a", + "GPP_H20", "n/a", "n/a", "n/a", + "GPP_H21", "n/a", "n/a", "n/a", + "GPP_H22", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_h_names) / 4, + .func_count = 4, + .pad_names = jasperlake_pch_group_h_names, +}; + +const char *const jasperlake_pch_group_spi_names[] = { + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MOSI_IO_0", "SPI0_MOSI_IO_0", + "SPI0_MISO_IO_0", "SPI0_MISO_IO_0", + "SPI0_TPM_CSB", "SPI0_TPM_CSB", + "SPI0_FLASH_0_CSB", "SPI0_FLASH_0_CSB", + "SPI0_FLASH_1_CSB", "SPI0_FLASH_1_CSB", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", +}; + +const struct gpio_group jasperlake_pch_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_spi_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_spi_names, +}; + +const char *const jasperlake_pch_group_r_names[] = { + "GPP_R00", "HDA_BCLK", "AVS_I2S0_SCLK", + "GPP_R01", "HDA_SYNC", "AVS_I2S0_SFRM", + "GPP_R02", "HDA_SDO", "AVS_I2S0_TXD", + "GPP_R03", "HDA_SDI0", "AVS_I2S0_RXD", + "GPP_R04", "HDA_RST_N", "n/a", + "GPP_R05", "HDA_SDI1", "AVS_I2S1_RXD", + "GPP_R06", "AVS_I2S1_SFRM", "n/a", + "GPP_R07", "AVS_I2S1_TXD", "n/a", +}; + +const struct gpio_group jasperlake_pch_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_r_names) / 3, + .func_count = 3, + .pad_names = jasperlake_pch_group_r_names, +}; + +const char *const jasperlake_pch_group_s_names[] = { + "GPP_S00", "n/a", "n/a", + "GPP_S01", "n/a", "n/a", + "GPP_S02", "n/a", "DMIC_CLK_1", + "GPP_S03", "n/a", "DMIC_DATA_1", + "GPP_S04", "SNDW1_CLK", "n/a", + "GPP_S05", "SNDW1_DATA", "n/a", + "GPP_S06", "n/a", "DMIC_CLK_0", + "GPP_S07", "n/a", "DMIC_DATA_0", +}; + +const struct gpio_group jasperlake_pch_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_s_names) / 3, + .func_count = 3, + .pad_names = jasperlake_pch_group_s_names, +}; + +const char *const jasperlake_pch_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIPB", "THRMTRIPB", + "PLTRST_CPUB", "PLTRST_CPUB", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", + "UFS_RESETB", "UFS_RESETB", + "CLKOUT_CPURTC", "CLKOUT_CPURTC", + "VCCST_PWRGD", "VCCST_PWRGD", + "C10_WAKE", "C10_WAKE", +}; + +const struct gpio_group jasperlake_pch_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_cpu_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_cpu_names, +}; + +const char *const jasperlake_pch_group_vgpio_pcie_names[] = { + "VGPIO_PCIE0", "VGPIO_PCIE0", + "VGPIO_PCIE1", "VGPIO_PCIE1", + "VGPIO_PCIE2", "VGPIO_PCIE2", + "VGPIO_PCIE3", "VGPIO_PCIE3", + "VGPIO_PCIE4", "VGPIO_PCIE4", + "VGPIO_PCIE5", "VGPIO_PCIE5", + "VGPIO_PCIE6", "VGPIO_PCIE6", + "VGPIO_PCIE7", "VGPIO_PCIE7", + "VGPIO_PCIE8", "VGPIO_PCIE8", + "VGPIO_PCIE9", "VGPIO_PCIE9", + "VGPIO_PCIE10", "VGPIO_PCIE10", + "VGPIO_PCIE11", "VGPIO_PCIE11", + "VGPIO_PCIE12", "VGPIO_PCIE12", + "VGPIO_PCIE13", "VGPIO_PCIE13", + "VGPIO_PCIE14", "VGPIO_PCIE14", + "VGPIO_PCIE15", "VGPIO_PCIE15", + "VGPIO_PCIE16", "VGPIO_PCIE16", + "VGPIO_PCIE17", "VGPIO_PCIE17", + "VGPIO_PCIE18", "VGPIO_PCIE18", + "VGPIO_PCIE19", "VGPIO_PCIE19", + "VGPIO_PCIE20", "VGPIO_PCIE20", + "VGPIO_PCIE21", "VGPIO_PCIE21", + "VGPIO_PCIE22", "VGPIO_PCIE22", + "VGPIO_PCIE23", "VGPIO_PCIE23", + "VGPIO_PCIE24", "VGPIO_PCIE24", + "VGPIO_PCIE25", "VGPIO_PCIE25", + "VGPIO_PCIE26", "VGPIO_PCIE26", + "VGPIO_PCIE27", "VGPIO_PCIE27", + "VGPIO_PCIE28", "VGPIO_PCIE28", + "VGPIO_PCIE29", "VGPIO_PCIE29", + "VGPIO_PCIE30", "VGPIO_PCIE30", + "VGPIO_PCIE31", "VGPIO_PCIE31", + "VGPIO_PCIE32", "VGPIO_PCIE32", + "VGPIO_PCIE33", "VGPIO_PCIE33", + "VGPIO_PCIE34", "VGPIO_PCIE34", + "VGPIO_PCIE35", "VGPIO_PCIE35", + "VGPIO_PCIE36", "VGPIO_PCIE36", + "VGPIO_PCIE37", "VGPIO_PCIE37", + "VGPIO_PCIE38", "VGPIO_PCIE38", + "VGPIO_PCIE39", "VGPIO_PCIE39", + "VGPIO_PCIE40", "VGPIO_PCIE40", + "VGPIO_PCIE41", "VGPIO_PCIE41", + "VGPIO_PCIE42", "VGPIO_PCIE42", + "VGPIO_PCIE43", "VGPIO_PCIE43", + "VGPIO_PCIE44", "VGPIO_PCIE44", + "VGPIO_PCIE45", "VGPIO_PCIE45", + "VGPIO_PCIE46", "VGPIO_PCIE46", + "VGPIO_PCIE47", "VGPIO_PCIE47", + "VGPIO_PCIE48", "VGPIO_PCIE48", + "VGPIO_PCIE49", "VGPIO_PCIE49", + "VGPIO_PCIE50", "VGPIO_PCIE50", + "VGPIO_PCIE51", "VGPIO_PCIE51", + "VGPIO_PCIE52", "VGPIO_PCIE52", + "VGPIO_PCIE53", "VGPIO_PCIE53", + "VGPIO_PCIE54", "VGPIO_PCIE54", + "VGPIO_PCIE55", "VGPIO_PCIE55", + "VGPIO_PCIE56", "VGPIO_PCIE56", + "VGPIO_PCIE57", "VGPIO_PCIE57", + "VGPIO_PCIE58", "VGPIO_PCIE58", + "VGPIO_PCIE59", "VGPIO_PCIE59", + "VGPIO_PCIE60", "VGPIO_PCIE60", + "VGPIO_PCIE61", "VGPIO_PCIE61", + "VGPIO_PCIE62", "VGPIO_PCIE62", + "VGPIO_PCIE63", "VGPIO_PCIE63", + "VGPIO_PCIE64", "VGPIO_PCIE64", + "VGPIO_PCIE65", "VGPIO_PCIE65", + "VGPIO_PCIE66", "VGPIO_PCIE66", + "VGPIO_PCIE67", "VGPIO_PCIE67", + "VGPIO_PCIE68", "VGPIO_PCIE68", + "VGPIO_PCIE69", "VGPIO_PCIE69", + "VGPIO_PCIE70", "VGPIO_PCIE70", + "VGPIO_PCIE71", "VGPIO_PCIE71", + "VGPIO_PCIE72", "VGPIO_PCIE72", + "VGPIO_PCIE73", "VGPIO_PCIE73", + "VGPIO_PCIE74", "VGPIO_PCIE74", + "VGPIO_PCIE75", "VGPIO_PCIE75", + "VGPIO_PCIE76", "VGPIO_PCIE76", + "VGPIO_PCIE77", "VGPIO_PCIE77", + "VGPIO_PCIE78", "VGPIO_PCIE78", + "VGPIO_PCIE79", "VGPIO_PCIE79", +}; +const struct gpio_group jasperlake_pch_group_vgpio_pcie = { + .display = "------- GPIO Group VGPIO_PCIE -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_vgpio_pcie_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_vgpio_pcie_names, +}; + +const char *const jasperlake_pch_group_vgpio_usb_names[] = { + "VGPIO_USB0", "VGPIO_USB0", + "VGPIO_USB1", "VGPIO_USB1", + "VGPIO_USB2", "VGPIO_USB2", + "VGPIO_USB3", "VGPIO_USB3", + "VGPIO_USB4", "VGPIO_USB4", + "VGPIO_USB5", "VGPIO_USB5", + "VGPIO_USB6", "VGPIO_USB6", + "VGPIO_USB7", "VGPIO_USB7", + "VGPIO_USB8", "VGPIO_USB8", + "VGPIO_USB9", "VGPIO_USB9", + "VGPIO_USB10", "VGPIO_USB10", + "VGPIO_USB11", "VGPIO_USB11", +}; + +const struct gpio_group jasperlake_pch_group_vgpio_usb = { + .display = "------- GPIO Group VGPIO_USB -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_vgpio_usb_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_vgpio_usb_names, +}; + +const char *const jasperlake_pch_vgpio_lnk_dn_names[] = { + "VGPIO_LNK_DN_0", "VGPIO_LNK_DN_0", + "VGPIO_LNK_DN_1", "VGPIO_LNK_DN_1", + "VGPIO_LNK_DN_2", "VGPIO_LNK_DN_2", + "VGPIO_LNK_DN_3", "VGPIO_LNK_DN_3", +}; + +const struct gpio_group jasperlake_pch_vgpio_lnk_dn = { + .display = "------- GPIO Group VGPIO_LNK -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_vgpio_lnk_dn_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_vgpio_lnk_dn_names, +}; + +const char *const jasperlake_pch_group_vgpio_names [] ={ + "VGPIO0", "VGPIO0", + "VGPIO3", "VGPIO3", + "VGPIO4", "VGPIO4", + "VGPIO5", "VGPIO5", + "VGPIO6", "VGPIO6", + "VGPIO7", "VGPIO7", + "VGPIO8", "VGPIO8", + "VGPIO9", "VGPIO9", + "VGPIO10", "VGPIO10", + "VGPIO11", "VGPIO11", + "VGPIO12", "VGPIO12", + "VGPIO13", "VGPIO13", + "VGPIO18", "VGPIO18", + "VGPIO19", "VGPIO19", + "VGPIO20", "VGPIO20", + "VGPIO21", "VGPIO21", + "VGPIO22", "VGPIO22", + "VGPIO23", "VGPIO23", + "VGPIO24", "VGPIO24", + "VGPIO25", "VGPIO25", + "VGPIO30", "VGPIO30", + "VGPIO31", "VGPIO31", + "VGPIO32", "VGPIO32", + "VGPIO33", "VGPIO33", + "VGPIO34", "VGPIO34", + "VGPIO35", "VGPIO35", + "VGPIO36", "VGPIO36", + "VGPIO37", "VGPIO37", + "VGPIO39", "VGPIO39", +}; + +const struct gpio_group jasperlake_pch_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_vgpio_names, +}; + +const char *const jasperlake_pch_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "PMC_ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PWRBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "INPUT3VSEL", "INPUT3VSEL", + "SLP_SUS#", "SLP_SUS#", + "WAKE#", "WAKE#", + "DRAM_RESET#", "DRAM_RESET#", +}; + +const struct gpio_group jasperlake_pch_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(jasperlake_pch_group_gpd_names) / 2, + .func_count = 2, + .pad_names = jasperlake_pch_group_gpd_names, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 1 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_0_groups[] = { + &jasperlake_pch_group_g, +}; + +const struct gpio_community jasperlake_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(jasperlake_community_0_groups), + .groups = jasperlake_community_0_groups, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 2 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_1_groups[] = { + &jasperlake_pch_hvcmos, + &jasperlake_pch_group_e, + &jasperlake_pch_jtag, + &jasperlake_pch_vgpio_lnk_dn, +}; + +const struct gpio_community jasperlake_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(jasperlake_community_1_groups), + .groups = jasperlake_community_1_groups, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 3 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_2_groups[] = { + &jasperlake_pch_group_cpu, + &jasperlake_pch_group_vgpio_pcie, + &jasperlake_pch_group_vgpio_usb, +}; + +const struct gpio_community jasperlake_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(jasperlake_community_2_groups), + .groups = jasperlake_community_2_groups, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 4 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_3_groups[] = { + &jasperlake_pch_group_gpd, +}; + +const struct gpio_community jasperlake_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(jasperlake_community_3_groups), + .groups = jasperlake_community_3_groups, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 5 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_4_groups[] = { + &jasperlake_pch_group_h, + &jasperlake_pch_group_d, + &jasperlake_pch_group_vgpio, + &jasperlake_pch_group_c, +}; + +const struct gpio_community jasperlake_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(jasperlake_community_4_groups), + .groups = jasperlake_community_4_groups, +}; + +/* ------------------------------------------------------------ */ +/* GPIO Group 6 */ +/* ------------------------------------------------------------ */ +const struct gpio_group *const jasperlake_community_5_groups[] = { + &jasperlake_pch_group_f, + &jasperlake_pch_group_spi, + &jasperlake_pch_group_b, + &jasperlake_pch_group_a, + &jasperlake_pch_group_s, + &jasperlake_pch_group_r, +}; + +const struct gpio_community jasperlake_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(jasperlake_community_5_groups), + .groups = jasperlake_community_5_groups, +}; + +const struct gpio_community *const jasperlake_pch_communities[] = { + &jasperlake_community_0, + &jasperlake_community_1, + &jasperlake_community_2, + &jasperlake_community_3, + &jasperlake_community_4, + &jasperlake_community_5, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 92a981a..e627570 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -405,6 +405,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM790, "WM790" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM770, "HM770" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL, "Elkhart Lake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JSL, "Jasper Lake" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 02c1692..f5b90ba 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -298,6 +298,7 @@ #define PCI_DEVICE_ID_INTEL_RPL_P 0x519d #define PCI_DEVICE_ID_INTEL_EHL 0x4b00 +#define PCI_DEVICE_ID_INTEL_JSL 0x4d87 /* untested, but almost identical to D-series */ #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index d1c5b27..52c59ae 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -154,6 +154,7 @@ case PCI_DEVICE_ID_INTEL_ADL_M: case PCI_DEVICE_ID_INTEL_RPL_P: case PCI_DEVICE_ID_INTEL_EHL: + case PCI_DEVICE_ID_INTEL_JSL: case PCI_DEVICE_ID_INTEL_EBG: sbbar_phys = 0xfd000000; use_p2sb = false; -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 24 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/volteer/var/delbin: Add new memory support
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74556 ) Change subject: mb/google/volteer/var/delbin: Add new memory support ...................................................................... mb/google/volteer/var/delbin: Add new memory support Add the new memory support: Samsung K4UBE3D4AB-MGCL BUG=b:274373361 BRANCH=firmware-volteer-13672.B TEST=FW_NAME=delbin emerge-volteer coreboot Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ie88c25b4b0f88ed299711f2b6b94006d5301554c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74556 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc M src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt 3 files changed, 26 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc index 625c149..1db15d4 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/delbin/memory/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen TGL lp4x src/mainboard/google/volteer/variants/delbin/memory src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt +# /tmp/go-build024059340/b001/exe/part_id_gen TGL lp4x src/mainboard/google/volteer/variants/delbin/memory/ src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt index c3249fd..ce366e8 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/delbin/memory/dram_id.generated.txt @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen TGL lp4x src/mainboard/google/volteer/variants/delbin/memory src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt +# /tmp/go-build024059340/b001/exe/part_id_gen TGL lp4x src/mainboard/google/volteer/variants/delbin/memory/ src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt index b99b811..f621414 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/delbin/memory/mem_parts_used.txt @@ -2,3 +2,4 @@ MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE H9HCNNNCPMMLXR-NEE +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/74556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie88c25b4b0f88ed299711f2b6b94006d5301554c Gerrit-Change-Number: 74556 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/myst: Update GPIO names
by Mark Hasemeyer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Karthik Ramasubramanian. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74596 ) Change subject: mb/google/myst: Update GPIO names ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ad4618eb6d897807d26c9bf8f2a090b5c9020c2 Gerrit-Change-Number: 74596 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:18:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:16:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74615 ) Change subject: soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb ...................................................................... soc/amd/common/cpu/noncar/early_cache: use get_top_of_mem_below_4gb Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74615 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/early_cache.c 1 file changed, 17 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c index 4bba172..2ff8760 100644 --- a/src/soc/amd/common/block/cpu/noncar/early_cache.c +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -20,7 +20,6 @@ */ void early_cache_setup(void) { - msr_t top_mem; msr_t sys_cfg; msr_t mtrr_def_type; msr_t fixed_mtrr_ram; @@ -34,7 +33,6 @@ var_mtrr_context_init(&mtrr_ctx.ctx); mtrr_ctx.ctx.max_var_mtrrs = MIN(MAX_VAR_MTRR_USE, mtrr_ctx.ctx.max_var_mtrrs); - top_mem = rdmsr(TOP_MEM); /* Enable RdDram and WrDram attributes in fixed MTRRs. */ sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -61,7 +59,8 @@ wrmsr(SYSCFG_MSR, sys_cfg); - var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8 * MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(get_top_of_mem_below_4gb(), 8 * MiB), + MTRR_TYPE_WRBACK); /* Always mark the 16 MByte right below the 4 GB boundary as WRPROT */ var_mtrr_set(&mtrr_ctx.ctx, FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); -- To view, visit https://review.coreboot.org/c/coreboot/+/74615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc9e5ad8954c6203fc4762aa976bba7e8ea16159 Gerrit-Change-Number: 74615 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74614 ) Change subject: soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb ...................................................................... soc/amd/stoneyridge/memmap: use get_top_of_mem_below_4gb Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74614 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/memmap.c 1 file changed, 16 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 8f73a8c..32d6d96 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -13,9 +13,7 @@ uintptr_t cbmem_top_chipset(void) { - msr_t tom = rdmsr(TOP_MEM); - - if (!tom.lo) + if (!get_top_of_mem_below_4gb()) return 0; /* 8MB alignment to keep MTRR usage low */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic673deb725a541c7535ae769f589cd82ea42a561 Gerrit-Change-Number: 74614 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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