coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74658/comment/9375e804_721c015e PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device : pointers were added right after the xhci_0 and xhci_1 controller device : pointers. Maybe say why? Should a similar comment be added to the source file? Nobody's going to look at the commit message unless they're debugging an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:39:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74657 ) Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:36:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74656 ) Change subject: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Gerrit-Change-Number: 74656 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:35:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74655 ) Change subject: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Gerrit-Change-Number: 74655 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74527 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ...................................................................... soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=b:277997811 TEST=Build Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 34 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 055e125..97b7ec1 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -11,19 +11,19 @@ device pci 01.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end - device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end - device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end - device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end + device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end device pci 03.0 on end # Dummy Host Bridge, do not disable device pci 03.1 alias usb4_pcie_bridge_0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/74527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Gerrit-Change-Number: 74527 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Eric Lai, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74527 ) Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Could you help add b:277997811 here? Thanks, I didn't even know that bug existed. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/74527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Gerrit-Change-Number: 74527 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:32:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Fred Reitberger, Felix Held. Martin Roth has uploaded a new patch set (#2) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/74527 ) Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off ...................................................................... soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=b:277997811 TEST=Build Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 30 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74527/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f Gerrit-Change-Number: 74527 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: replace some magic numbers
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74617 ) Change subject: cpu/amd/pi/00730F01/fixme: replace some magic numbers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec Gerrit-Change-Number: 74617 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:28:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/cpu/amd/pi/00730F01/fixme.c: https://review.coreboot.org/c/coreboot/+/74616/comment/b266193c_dbaa7221 PS1, Line 19: 0x00fedf00 > Should this be changed to 0xfedf0000 for our functions? It looks like it gets fixed in the next pat […] Nevermind, it looks like we're good. -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:26:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74526 ) Change subject: soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off ...................................................................... soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=None TEST=Don't see the "PCI: Leftover static devices:" warning for these in the boot console. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb 2 files changed, 36 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index b4efdf5..c1da13c 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -10,10 +10,10 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 2ecb2405..fe97cf8 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -10,12 +10,12 @@ device pci 01.0 on end # Dummy Host Bridge device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A -- To view, visit https://review.coreboot.org/c/coreboot/+/74526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Gerrit-Change-Number: 74526 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2023