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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 40:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/e1419283_258d2948
PS40, Line 51: GEN3
> As Felix noted, we should be able to set this to `GEN_MAX`, and remove the TODO here: […]
`lspci -v` should show you the speed.
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 40:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/432cf903_8dcbdfbd
PS40, Line 51: GEN3
As Felix noted, we should be able to set this to `GEN_MAX`, and remove the TODO here:
https://review.coreboot.org/c/coreboot/+/74112/comments/56081bd9_e3990be5
We should still validate it's actually training at GEN4 once it's available (somehow), so the bug itself should probably be updated to track that validation of GEN4 (rather than enabling).
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Change subject: mb/google/rex: Add RTD3 support for SSD
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> We will validate and let you know.
I observed s0ix working with this CL.
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Change subject: Documentation/measured_boot.md: fix SRTM/DRTM explanations
......................................................................
Patch Set 13: Code-Review+2
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Change subject: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74658/comment/7932ae92_a215475f
PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device
: pointers were added right after the xhci_0 and xhci_1 controller device
: pointers.
> Maybe say why? Should a similar comment be added to the source file? Nobody's going to look at the […]
Definitely agree with Martin. I started looking into why it was not added to SOC_XHCI_3/4 similar to SMI/SCI map. Then later found that saving of XHCI PCI resources does not expect a hole in the list of XHCI devices. From that standpoint a comment is really helpful.
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Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
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Patch Set 3: Code-Review+2
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Change subject: soc/ibm/power9/*: add file structure for SOC
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67062/comment/d65bd190_aa490735
PS3, Line 10: Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
> I agree, I was not the author of this commit.
Updated, but didn't add myself. I don't think committing requires `Signed-off-by:`.
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Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Created b/279144932 to look at refactoring.
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Hello build bot (Jenkins), Igor Bagnucki, Michał Żygowski, Michał Kopeć, Krystian Hebel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/67062
to look at the new patch set (#4).
Change subject: soc/ibm/power9/*: add file structure for SOC
......................................................................
soc/ibm/power9/*: add file structure for SOC
Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3
Signed-off-by: Igor Bagnucki <bagnucki02(a)gmail.com>
---
A src/soc/ibm/Kconfig
A src/soc/ibm/power9/Kconfig
A src/soc/ibm/power9/Makefile.inc
A src/soc/ibm/power9/bootblock.c
A src/soc/ibm/power9/chip.c
A src/soc/ibm/power9/romstage.c
A src/soc/ibm/power9/timer.c
7 files changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/67062/4
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