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Change subject: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74277 )
(
11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/myst: Enable mp2 device
......................................................................
mb/google/myst: Enable mp2 device
The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to
the device and since the bridge doesn't have enough MMIO space reserved,
the Linux kernel can't assign resources to it. Enable the mp2 device in
the mainboard's devicetree so that it gets its resources assigned by
coreboot.
BUG=b:277217097
TEST=builds
Change-Id: I21885c51ff08846b456675090946f381843ef5e6
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
1 file changed, 27 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 669d6ec..9fc5bfe 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -132,6 +132,7 @@
end
end
device ref acp on end # Audio Processor (ACP)
+ device ref mp2 on end # Sensor Fusion Hub (MP2)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref usb4_xhci_0 on
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Change subject: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
......................................................................
Patch Set 2: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74276 )
(
10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/myst: Enable audio co-processor in devicetree
......................................................................
mb/google/myst: Enable audio co-processor in devicetree
Enable the audio co-processor in the device tree.
BUG=b:277214614
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74276
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Karthik Ramasubramanian: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 085e464..669d6ec 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -131,6 +131,7 @@
end
end
end
+ device ref acp on end # Audio Processor (ACP)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref usb4_xhci_0 on
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Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 )
Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 40:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/a42ba28a_a66e4c15
PS40, Line 41: .gpio_group_id = GPIO_29,
> GPIOs should be named pending: https://review.coreboot. […]
GPIO_29 will still be valid even after the renaming. I'm not going to close the bug with the above associated CL until it lands, and I'm able to update all of these. Since there's some debate over how or how much of the above CL should land, this is a NO-OP for now.
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74659 )
Change subject: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
......................................................................
cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
Now that the code is in a much better shape and uses native coreboot
functionality to perform the initialization, rename the file from
fixme.c to cpu_io_init.c to be more descriptive of what it does.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318
---
M src/cpu/amd/pi/00730F01/Makefile.inc
R src/cpu/amd/pi/00730F01/cpu_io_init.c
2 files changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74659/1
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
index 51f90ef..ae5a20b 100644
--- a/src/cpu/amd/pi/00730F01/Makefile.inc
+++ b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
-romstage-y += fixme.c
+romstage-y += cpu_io_init.c
-ramstage-y += fixme.c
ramstage-y += chip_name.c
+ramstage-y += cpu_io_init.c
ramstage-y += model_16_init.c
ramstage-y += update_microcode.c
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/cpu_io_init.c
similarity index 100%
rename from src/cpu/amd/pi/00730F01/fixme.c
rename to src/cpu/amd/pi/00730F01/cpu_io_init.c
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Change subject: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
LGTM
Fingers crossed the eMMC CLKREQ line works better on both boards.
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Change subject: mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
LGTM
Fingers crossed the eMMC CLKREQ line works better on both boards.
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Change subject: Documentation/mainboard/hp: Add more about internal flashing
......................................................................
Patch Set 10:
(3 comments)
File Documentation/mainboard/hp/compaq_8200_sff.md:
https://review.coreboot.org/c/coreboot/+/74248/comment/b0f5df8d_7b85af78
PS9, Line 81: need fix
> need *to* fix
Done
https://review.coreboot.org/c/coreboot/+/74248/comment/f618d23d_bb53af7a
PS9, Line 86: filesystem
> You can drop "filesystem" as CBFS stands for "coreboot filesystem"
Done
https://review.coreboot.org/c/coreboot/+/74248/comment/5d30c452_0319eccc
PS9, Line 89: descrtiptor
> spelling: descriptor
Done
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