coreboot-gerrit April 2023

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[S] Change in coreboot[master]: drivers/intel/ish: Hook get ISH version into `.final`
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74209 ) ( 18 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/ish: Hook get ISH version into `.final` ...................................................................... drivers/intel/ish: Hook get ISH version into `.final` This patch creates .final hook to call into get ISH version function if platform has required config (`SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION`) support. BUG=b:273661726 TEST=The ISHC version, 5.4.2.7779, was retrieved on the google/nivviks. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74209 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/ish/ish.c 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index a232217..0415af0 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -2,9 +2,11 @@ #include <acpi/acpi_device.h> #include <acpi/acpigen.h> +#include <cbmem.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/cse.h> #include "chip.h" static void ish_fill_ssdt_generator(const struct device *dev) @@ -46,6 +48,25 @@ dev->ops = &intel_ish_ops; } +static void intel_ish_get_version(void) +{ + struct cse_fw_partition_info *version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); + if (version == NULL) + return; + + printk(BIOS_DEBUG, "ISH version: %d.%d.%d.%d\n", + version->ish_partition_info.cur_ish_fw_version.major, + version->ish_partition_info.cur_ish_fw_version.minor, + version->ish_partition_info.cur_ish_fw_version.hotfix, + version->ish_partition_info.cur_ish_fw_version.build); +} + +static void intel_ish_final(struct device *dev) +{ + if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + intel_ish_get_version(); +} + /* Copy of default_pci_ops_dev with scan_bus addition */ static const struct device_operations pci_ish_device_ops = { .read_resources = pci_dev_read_resources, @@ -54,6 +75,7 @@ .init = pci_dev_init, .scan_bus = &scan_generic_bus, /* Non-default */ .ops_pci = &pci_dev_ops_pci, + .final = intel_ish_final, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/74209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8 Gerrit-Change-Number: 74209 Gerrit-PatchSet: 23 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74208 ) Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM ...................................................................... soc/intel/cmn/cse: Store ISH firmware version into CBMEM The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74208 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 75 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f7ebed0..4cc4f51 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1236,6 +1236,52 @@ return send_get_fpt_partition_info_cmd(id, resp); } +/* + * Helper function to read ISH version from CSE FPT using HECI command. + * + * The HECI command only be executed after memory has been initialized. + * This is because the command relies on resources that are not available + * until DRAM initialization command has been sent. + */ +static void store_ish_version(void) +{ + if (!ENV_RAMSTAGE) + return; + + if (vboot_recovery_mode_enabled()) + return; + + struct cse_fw_partition_info *version; + size_t size = sizeof(struct fw_version); + version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); + if (version == NULL) + return; + + /* + * Compare if stored cse version (from the previous boot) is same as current + * running cse version. + */ + if (memcmp(&version->ish_partition_info.prev_cse_fw_version, + &version->cur_cse_fw_version, sizeof(struct fw_version))) { + /* + * Current running CSE version is different than previous stored CSE version + * which could be due to CSE update or rollback, hence, need to send ISHC + * partition info cmd to know the currently running ISH version. + */ + + struct fw_version_resp resp; + if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { + /* Update stored cse version with current version */ + memcpy(&(version->ish_partition_info.prev_cse_fw_version), + &(version->cur_cse_fw_version), size); + + /* Since cse version has been updated, ish version needs to be updated. */ + memcpy(&(version->ish_partition_info.cur_ish_fw_version), + &(resp.manifest_data.version), size); + } + } +} + static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) @@ -1245,12 +1291,14 @@ cse_fw_sync(); /* - * Store the CSE RW Firmware Version into CBMEM if ISH partition + * Store the CSE/ISH RW Firmware Version into CBMEM if ISH partition * is available */ if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && - soc_is_ish_partition_enabled()) + soc_is_ish_partition_enabled()) { store_cse_rw_fw_version(); + store_ish_version(); + } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_misc_ops, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/74208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Gerrit-Change-Number: 74208 Gerrit-PatchSet: 26 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74256 ) Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM ...................................................................... {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 131 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index fa5c8d9..4162d84 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -85,6 +85,7 @@ #define CBMEM_ID_MEM_CHIP_INFO 0x5048434D #define CBMEM_ID_AMD_STB 0x5f425453 #define CBMEM_ID_AMD_MP2 0x5f32504d +#define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -163,5 +164,6 @@ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ { CBMEM_ID_AMD_STB, "AMD STB"},\ - { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"} + { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ + { CBMEM_ID_CSE_PARTITION_VERSION, "CSE PARTITION VERSION"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 33d703f..73cb51bc 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,27 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + bool + default n + depends on DRIVERS_INTEL_ISH + help + This configuration option stores CSE FPT partitions' version in CBMEM memory. + This information can be used to identify the currently running firmware partition + version. + + The cost of sending HECI command to read the CSE FPT is significant (~200ms) + hence, the idea is to read the CSE RW version on every cold reset (to cover + the CSE update scenarios) and store into CBMEM to avoid the cost of resending + the HECI command in all consecutive warm boots. + + Later boot stages can just read the CBMEM ID to retrieve the ISH version if + required. + + Additionally, ensure this feature is platform specific hence, only enabled + for the platform that would like to store the ISH version into the CBMEM and + parse to perform some additional work. + config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 14a7381..f7ebed0 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1159,6 +1159,26 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } +/* + * Helper function that stores current CSE firmware version to CBMEM memory, + * except during recovery mode. + */ +static void store_cse_rw_fw_version(void) +{ + if (vboot_recovery_mode_enabled()) + return; + + struct get_bp_info_rsp cse_bp_info; + if (!cse_get_bp_info(&cse_bp_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); + return; + } + const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); + struct cse_fw_partition_info *version; + version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); + memcpy(&(version->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); +} + static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1216,13 +1236,21 @@ return send_get_fpt_partition_info_cmd(id, resp); } -static void ramstage_cse_fw_sync(void *unused) +static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) return; if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); + + /* + * Store the CSE RW Firmware Version into CBMEM if ISH partition + * is available + */ + if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && + soc_is_ish_partition_enabled()) + store_cse_rw_fw_version(); } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_misc_ops, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6b708ca..f3a7f83 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -144,6 +144,18 @@ struct flash_partition_data manifest_data; }; +/* ISHC version */ +struct cse_fw_ish_version_info { + struct fw_version prev_cse_fw_version; + struct fw_version cur_ish_fw_version; +}; + +/* CSE and ISHC version */ +struct cse_fw_partition_info { + struct fw_version cur_cse_fw_version; + struct cse_fw_ish_version_info ish_partition_info; +}; + /* CSE RX and TX error status */ enum cse_tx_rx_status { /* @@ -502,6 +514,27 @@ void soc_disable_heci1_using_pcr(void); /* + * SoC override API to identify if ISH Firmware existed inside CSE FPT. + * + * This override is required to avoid making default call into non-ISH + * supported SKU to attempt to retrieve ISH version which would results into + * increased boot time by 100ms+. + * + * Ideally SoC with UFS enabled would like to keep ISH enabled as well, hence + * identifying the UFS enabled device is enough to conclude if ISH partition is + * available. + */ +#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +bool soc_is_ish_partition_enabled(void); +#else +static inline bool soc_is_ish_partition_enabled(void) +{ + /* Default implementation, ISH not enabled. */ + return false; +} +#endif + +/* * Injects CSE timestamps into cbmem timestamp table. SoC code needs to * implement it since timestamp definitions differ from SoC to SoC. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Gerrit-Change-Number: 74256 Gerrit-PatchSet: 22 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74658/comment/5cbd03b1_57880b21 PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device : pointers were added right after the xhci_0 and xhci_1 controller device : pointers. > Definitely agree with Martin. […] ah, ok, wasn't sure about this requirement of the xhci pci code; pinged Robert to look into that. do yo uhave any suggestions for the comments? is adding add a /* XHCI3 */ comment to the #define SOC_XHCI_2 DEV_PTR(usb4_xhci_0) sufficient? same for the next one -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 17:17:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74657 ) Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 17:15:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/glinda: drop code for non-existing eMMC controller
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74662 ) Change subject: soc/amd/glinda: drop code for non-existing eMMC controller ...................................................................... soc/amd/glinda: drop code for non-existing eMMC controller Glinda doesn't have an eMMC controller and also doesn't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Glinda. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49ead01075780ea97dae99a36632f7659fd00587 --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/chipset.cb M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/glinda/include/soc/aoac_defs.h M src/soc/amd/glinda/include/soc/iomap.h 7 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74662/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 77be8af..d80eb3f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -46,7 +46,6 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC - select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl index 17b7cd7..dfbf5c7 100644 --- a/src/soc/amd/glinda/acpi/pci_int_defs.asl +++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl @@ -22,9 +22,6 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ - Offset (0x43), - PMMC, 0x00000008, /* Index 0x43: eMMC */ - Offset (0x62), PGPI, 0x00000008, /* Index 0x62: GPIO */ @@ -51,9 +48,6 @@ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ - Offset (0xC3), - IMMC, 0x00000008, /* Index 0xC3: eMMC */ - Offset (0xE2), IGPI, 0x00000008, /* Index 0xE2: GPIO */ diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index d54bae0..ad477c7 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -95,5 +95,4 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 5608e7c..93597c9 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -53,7 +53,6 @@ { PIRQ_GPIOA, "GPIOa" }, { PIRQ_GPIOB, "GPIOb" }, { PIRQ_GPIOC, "GPIOc" }, - { PIRQ_EMMC, "eMMC" }, { PIRQ_GPP0, "GPP0" }, { PIRQ_GPP1, "GPP1" }, { PIRQ_GPP2, "GPP2" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index 7f9b1da..c7ff65b 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -40,9 +40,7 @@ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x42 reserved */ -#define PIRQ_EMMC 0x43 /* eMMC */ -/* 0x44-0x4f reserved */ +/* 0x24-0x4f reserved */ #define PIRQ_GPP0 0x50 /* GPPInt0 */ #define PIRQ_GPP1 0x51 /* GPPInt1 */ #define PIRQ_GPP2 0x52 /* GPPInt2 */ diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h index 0edd823..b923ab3 100644 --- a/src/soc/amd/glinda/include/soc/aoac_defs.h +++ b/src/soc/amd/glinda/include/soc/aoac_defs.h @@ -20,6 +20,5 @@ #define FCH_AOAC_DEV_UART4 20 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -#define FCH_AOAC_DEV_EMMC 28 #endif /* AMD_GLINDA_AOAC_DEFS_H */ diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index b335b3f..30fff9f 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -36,9 +36,6 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 -#define APU_EMMC_BASE 0xfedd5000 -#define APU_EMMC_CONFIG_BASE 0xfedd5800 - #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/74662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49ead01075780ea97dae99a36632f7659fd00587 Gerrit-Change-Number: 74662 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix: drop defines for non-existing eMMC controller
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74661 ) Change subject: soc/amd/phoenix: drop defines for non-existing eMMC controller ...................................................................... soc/amd/phoenix: drop defines for non-existing eMMC controller Phoenix doesn't have an eMMC controller, so remove the remaining eMMC- related defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I412c968479d23deb7f2e060b26b4a56ec9c764f2 --- M src/soc/amd/phoenix/include/soc/aoac_defs.h M src/soc/amd/phoenix/include/soc/iomap.h 2 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74661/1 diff --git a/src/soc/amd/phoenix/include/soc/aoac_defs.h b/src/soc/amd/phoenix/include/soc/aoac_defs.h index 1dbfc48..96df50ba 100644 --- a/src/soc/amd/phoenix/include/soc/aoac_defs.h +++ b/src/soc/amd/phoenix/include/soc/aoac_defs.h @@ -18,6 +18,5 @@ #define FCH_AOAC_DEV_UART4 20 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -#define FCH_AOAC_DEV_EMMC 28 #endif /* AMD_PHOENIX_AOAC_DEFS_H */ diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index b12b48c..5e2c7c3 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -34,9 +34,6 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 -#define APU_EMMC_BASE 0xfedd5000 -#define APU_EMMC_CONFIG_BASE 0xfedd5800 - #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/74661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412c968479d23deb7f2e060b26b4a56ec9c764f2 Gerrit-Change-Number: 74661 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: drop code for non-existing eMMC controller
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74660 ) Change subject: soc/amd/mendocino: drop code for non-existing eMMC controller ...................................................................... soc/amd/mendocino: drop code for non-existing eMMC controller Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 --- M src/mainboard/amd/chausie/mainboard.c M src/mainboard/google/skyrim/mainboard.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/acpi/pci_int_defs.asl M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/fch.c M src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h M src/soc/amd/mendocino/include/soc/aoac_defs.h M src/soc/amd/mendocino/include/soc/iomap.h 10 files changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74660/1 diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c index 17c9d78..41e314a 100644 --- a/src/mainboard/amd/chausie/mainboard.c +++ b/src/mainboard/amd/chausie/mainboard.c @@ -33,7 +33,6 @@ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, { PIRQ_GPIO, 11, 11 }, { PIRQ_I2C0, 10, 10 }, { PIRQ_I2C1, 7, 7 }, diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 475e5cf..890c6b3 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -39,7 +39,6 @@ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, { PIRQ_GPIO, 11, 11 }, { PIRQ_I2C0, 10, 10 }, { PIRQ_I2C1, 7, 7 }, diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 91fd57d..41861ee 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -45,7 +45,6 @@ select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC - select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/mendocino/acpi/pci_int_defs.asl b/src/soc/amd/mendocino/acpi/pci_int_defs.asl index 6d19403..1b40e7a 100644 --- a/src/soc/amd/mendocino/acpi/pci_int_defs.asl +++ b/src/soc/amd/mendocino/acpi/pci_int_defs.asl @@ -20,9 +20,6 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */ - Offset (0x43), - PMMC, 0x00000008, /* Index 0x43: eMMC */ - Offset (0x62), PGPI, 0x00000008, /* Index 0x62: GPIO */ @@ -49,9 +46,6 @@ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ - Offset (0xC3), - IMMC, 0x00000008, /* Index 0xC3: eMMC */ - Offset (0xE2), IGPI, 0x00000008, /* Index 0xE2: GPIO */ diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index c1da13c..691cca0 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -90,5 +90,4 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index fe97cf8..fd31efe 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -93,5 +93,4 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index 5edbcc6..772cca0 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -52,7 +52,6 @@ { PIRQ_GPIOA, "GPIOa" }, { PIRQ_GPIOB, "GPIOb" }, { PIRQ_GPIOC, "GPIOc" }, - { PIRQ_EMMC, "eMMC" }, { PIRQ_GPP0, "GPP0" }, { PIRQ_GPP1, "GPP1" }, { PIRQ_GPP2, "GPP2" }, diff --git a/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h b/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h index 35e0d90..fec7aef 100644 --- a/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h @@ -38,9 +38,7 @@ #define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ #define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ #define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ -/* 0x24-0x42 reserved */ -#define PIRQ_EMMC 0x43 /* eMMC */ -/* 0x44-0x4f reserved */ +/* 0x24-0x4f reserved */ #define PIRQ_GPP0 0x50 /* GPPInt0 */ #define PIRQ_GPP1 0x51 /* GPPInt1 */ #define PIRQ_GPP2 0x52 /* GPPInt2 */ diff --git a/src/soc/amd/mendocino/include/soc/aoac_defs.h b/src/soc/amd/mendocino/include/soc/aoac_defs.h index 46fb318..5dcca03 100644 --- a/src/soc/amd/mendocino/include/soc/aoac_defs.h +++ b/src/soc/amd/mendocino/include/soc/aoac_defs.h @@ -18,6 +18,5 @@ #define FCH_AOAC_DEV_UART4 20 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -#define FCH_AOAC_DEV_EMMC 28 #endif /* AMD_MENDOCINO_AOAC_DEFS_H */ diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 1e1120c..859dfd5 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -34,9 +34,6 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 -#define APU_EMMC_BASE 0xfedd5000 -#define APU_EMMC_CONFIG_BASE 0xfedd5800 - #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/74660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Gerrit-Change-Number: 74660 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74656 ) Change subject: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Gerrit-Change-Number: 74656 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 17:10:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74655 ) Change subject: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Gerrit-Change-Number: 74655 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 17:09:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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