coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/brya: Enable RTD3 root port mutex for WWAN
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73382 ) Change subject: mb/google/brya: Enable RTD3 root port mutex for WWAN ...................................................................... mb/google/brya: Enable RTD3 root port mutex for WWAN This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb 6 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index e07fc72..e8cde58 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -419,6 +419,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on probe DB_LTE LTE_PCIE end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index e289fca..f8619c9 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -187,6 +187,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on probe DB_LTE LTE_PCIE end diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index c6cf489..81a808f 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -173,6 +173,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on probe DB_LTE LTE_PCIE end diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index d21b3e1..0677f82 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -419,6 +419,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on probe DB_LTE LTE_PCIE end diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb index 5916fc7..6d1207f 100644 --- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb @@ -262,6 +262,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on probe DB_LTE LTE_PCIE end diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 8751350..1100628 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -200,6 +200,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on end end chip drivers/wwan/fm -- To view, visit https://review.coreboot.org/c/coreboot/+/73382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1 Gerrit-Change-Number: 73382 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/link: Apply symmetry for EC events defines
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74602 ) Change subject: mb/google/link: Apply symmetry for EC events defines ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/link/ec.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174748): https://review.coreboot.org/c/coreboot/+/74602/comment/e3f537c7_fb68748f PS1, Line 11: #define MAINBOARD_EC_SCI_EVENTS \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/74602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d9d28963c97e780156d75b39deac069028866a Gerrit-Change-Number: 74602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 18:38:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] mb/google: Use chromeec_smi_sleep()
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74605 ) Change subject: [WIP] mb/google: Use chromeec_smi_sleep() ...................................................................... [WIP] mb/google: Use chromeec_smi_sleep() Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c 5 files changed, 16 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74605/1 diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 15dc7f7..561f5a5 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -50,25 +50,7 @@ break; } - switch (slp_typ) { - case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S4: - case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 5b42671..ec0c44d 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" -#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -56,25 +55,7 @@ break; } - switch (slp_typ) { - case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S4: - case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); /* Set LPC lines to low power in S3/S5. */ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) { diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index dc10a15..8e07a97 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> -#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include "ec.h" @@ -37,25 +36,7 @@ break; } - switch (slp_typ) { - case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S4: - case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(uint8_t apmc) diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index efc9486..863109e 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -11,7 +11,6 @@ #include <cpu/intel/haswell/haswell.h> /* Include EC functions */ -#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include "ec.h" @@ -48,25 +47,8 @@ break; } - switch (slp_typ) { - case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S4: - case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; + /* Does not handle ACPI_S4 */ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index f124935..bc43dd6 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -6,7 +6,6 @@ #include <cpu/x86/smm.h> #include "ec.h" -#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <soc/pm.h> @@ -42,25 +41,7 @@ break; } - switch (slp_typ) { - case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S4: - case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); /* Set LPC lines to low power in S3/S5. */ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) -- To view, visit https://review.coreboot.org/c/coreboot/+/74605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Gerrit-Change-Number: 74605 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] mb/google: Re-arrange mainboard_smi_sleep()
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74604 ) Change subject: [WIP] mb/google: Re-arrange mainboard_smi_sleep() ...................................................................... [WIP] mb/google: Re-arrange mainboard_smi_sleep() If we can change the order... can call chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/strago/smihandler.c 5 files changed, 55 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/74604/1 diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index bba9fc23..15dc7f7 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -44,14 +44,19 @@ switch (slp_typ) { case ACPI_S3: + case ACPI_S4: + case ACPI_S5: mainboard_disable_gpios(); + break; + } + switch (slp_typ) { + case ACPI_S3: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; + case ACPI_S4: case ACPI_S5: - mainboard_disable_gpios(); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 562a6bd..5b42671 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -40,15 +40,11 @@ switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + case ACPI_S4: case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - /* Disabling wake from SUS_GPIO1 (TOUCH INT) and * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not * valid S5 wake sources @@ -57,7 +53,18 @@ GPIO_WAKE_MASK_REG0); mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); write32(addr, read32(addr) & mask); + break; + } + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case ACPI_S4: + case ACPI_S5: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; } diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index affa3b0..dc10a15 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -32,11 +32,17 @@ switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + } + + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case ACPI_S4: case ACPI_S5: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 3ac2152..efc9486 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -38,23 +38,23 @@ switch (slp_typ) { case ACPI_S3: - /* Prevent leak from standby rail to WLAN rail in S3. */ + case ACPI_S4: + case ACPI_S5: + /* Prevent leak from standby rail to WLAN rail in S3/S4/S5. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); set_gpio(GPIO_PP3300_CODEC_EN, 0); /* Disable LTE */ set_gpio(GPIO_LTE_DISABLE_L, 0); + break; + } + switch (slp_typ) { + case ACPI_S3: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; case ACPI_S4: case ACPI_S5: - /* Prevent leak from standby rail to WLAN rail in S5. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); - set_gpio(GPIO_PP3300_CODEC_EN, 0); - /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); - /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 3daf3b6..f124935 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -37,11 +37,17 @@ switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + } + + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case ACPI_S4: case ACPI_S5: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); -- To view, visit https://review.coreboot.org/c/coreboot/+/74604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Gerrit-Change-Number: 74604 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] mb/google/link: Use chromeec_smi_sleep()
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Caveh Jalali, Boris Mittelberg. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74603 ) Change subject: [WIP] mb/google/link: Use chromeec_smi_sleep() ...................................................................... [WIP] mb/google/link: Use chromeec_smi_sleep() Board did not use MAINBOARD_EC_S5_WAKE attribute before. Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/google/chromeec/smihandler.c M src/mainboard/google/link/smihandler.c 2 files changed, 17 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74603/1 diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index 599a66e..5df39d3 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -40,9 +40,11 @@ while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) ; + printk(BIOS_DEBUG, "Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.\n"); while (google_chromeec_get_mkbp_event(&mkbp_event) == 0) ; + } void chromeec_set_usb_charge_mode(bool u0disable, bool u1disable) @@ -62,6 +64,7 @@ /* Enable wake events */ google_chromeec_set_wake_mask(s3_mask); break; + case ACPI_S4: case ACPI_S5: /* Enable wake events */ google_chromeec_set_wake_mask(s5_mask); diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index cc19d34..9c76c33 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -19,6 +19,7 @@ chromeec_smi_process_events(); } +/* test slp_typ */ void mainboard_smi_sleep(u8 slp_typ) { bool u0disable = 0, u1disable = 0; @@ -27,16 +28,7 @@ usb_charge_mode_from_gnvs(slp_typ, &u0disable, &u1disable); chromeec_set_usb_charge_mode(u0disable, u1disable); - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != EC_HOST_EVENT_NONE) - ; - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) -- To view, visit https://review.coreboot.org/c/coreboot/+/74603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2 Gerrit-Change-Number: 74603 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/link: Apply symmetry for EC events defines
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74602 ) Change subject: mb/google/link: Apply symmetry for EC events defines ...................................................................... mb/google/link: Apply symmetry for EC events defines All other boards use MAINBOARD_ prefix instead of board name. Change-Id: I97d9d28963c97e780156d75b39deac069028866a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/link/ec.c M src/mainboard/google/link/ec.h M src/mainboard/google/link/smihandler.c 3 files changed, 24 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/74602/1 diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 2c2ed74..e18e878 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -8,10 +8,10 @@ void link_ec_init(void) { const struct google_chromeec_event_info info = { - .log_events = LINK_EC_LOG_EVENTS, - .sci_events = LINK_EC_SCI_EVENTS, - .s3_wake_events = LINK_EC_S3_WAKE_EVENTS, - .s5_wake_events = LINK_EC_S5_WAKE_EVENTS, + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; printk(BIOS_DEBUG, "%s\n", __func__); diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h index 78487d6..329ef08 100644 --- a/src/mainboard/google/link/ec.h +++ b/src/mainboard/google/link/ec.h @@ -8,7 +8,7 @@ #define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */ #define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ -#define LINK_EC_SCI_EVENTS \ +#define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ @@ -18,21 +18,21 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD)) -#define LINK_EC_SMI_EVENTS \ +#define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) /* EC can wake from S5 with lid or power button */ -#define LINK_EC_S5_WAKE_EVENTS \ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* EC can wake from S3 with lid or power button or key press */ -#define LINK_EC_S3_WAKE_EVENTS \ - (LINK_EC_S5_WAKE_EVENTS |\ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) /* Log EC wake events plus EC shutdown events */ -#define LINK_EC_LOG_EVENTS \ +#define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 4a9dfb0..951cabc 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -50,11 +50,11 @@ ; /* Enable wake events */ - google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS); + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - chromeec_smi_apmc(apmc, LINK_EC_SCI_EVENTS, LINK_EC_SMI_EVENTS); + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d9d28963c97e780156d75b39deac069028866a Gerrit-Change-Number: 74602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Lance Zhao, Caveh Jalali, Tim Wawrzynczak, Kyösti Mälkki, Boris Mittelberg. Hello Lance Zhao, build bot (Jenkins), Caveh Jalali, Paul Menzel, Tim Wawrzynczak, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74524 to look at the new patch set (#4). Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... [WIP] ACPI: Add usb_charge_mode_from_gnvs() Used together with (old API?) of ChromeEC to control USB port power for S3/S4/S5 sleep states. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi_pm.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/include/acpi/acpi_gnvs.h M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/Kconfig M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/Kconfig M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/Kconfig M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/strago/smihandler.c M src/soc/intel/broadwell/include/soc/nvs.h 24 files changed, 122 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/74524/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Robert Zieba (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74658/comment/f0d9d9f6_edcd2929 PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device : pointers were added right after the xhci_0 and xhci_1 controller device : pointers. > ah, ok, wasn't sure about this requirement of the xhci pci code; pinged Robert to look into that. […] The relevant code just doesn't support holes in the device list. In particular, the XHCI wake event logging code uses the PCI resources that are stored in SMRAM. The resource store code has no concept of gaps in the device list, nor should it IMHO. So any change would have to be done in the XHCI-specific code. The XHCI wake events in the elog do use the index into `SOC_XHCI_DEVICES` as the XHCI controller number. So that could be confusing if we did ever have both an `xhci_2` and `usb4_xhci_0`. But overall, I don't think that's a big issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 18:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable asynchronous End-Of-Post
by Subrata Banik (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74562 ) Change subject: mb/google/rex: Enable asynchronous End-Of-Post ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74562/comment/d4184a65_e2897a48 PS1, Line 92: if !BOARD_GOOGLE_REX_COMMON > > would it be possible to use "if !SOC_INTEL_CSE_SEND_EOP_ASYNC" instead to avoid using board-specif […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Gerrit-Change-Number: 74562 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 18:15:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/glinda: drop code for non-existing eMMC controller
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74662 ) Change subject: soc/amd/glinda: drop code for non-existing eMMC controller ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49ead01075780ea97dae99a36632f7659fd00587 Gerrit-Change-Number: 74662 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 17:53:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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