coreboot-gerrit April 2023

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[S] Change in coreboot[master]: arch/riscv: Use updated name for sbadaddr
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Arthur Heymans, Philipp Hug, Angel Pons, ron minnich. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63073 ) Change subject: arch/riscv: Use updated name for sbadaddr ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: CB:74569 was merged instead -- To view, visit https://review.coreboot.org/c/coreboot/+/63073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Gerrit-Change-Number: 63073 Gerrit-PatchSet: 26 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 20:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/riscv/trap_handler.c: Use new names for CSR
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74569 ) Change subject: arch/riscv/trap_handler.c: Use new names for CSR ...................................................................... arch/riscv/trap_handler.c: Use new names for CSR sbadaddr and mbadaddr are deprecated names. This fixes compilation with clang. Change-Id: I5c8fa82b6131dec10f55e8ebcf36b34e30b57bad Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74569 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f5953d3..8cb27de 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -150,7 +150,7 @@ /* This function used to redirect trap to s-mode. */ void redirect_trap(void) { - write_csr(sbadaddr, read_csr(mbadaddr)); + write_csr(stval, read_csr(mtval)); write_csr(sepc, read_csr(mepc)); write_csr(scause, read_csr(mcause)); write_csr(mepc, read_csr(stvec)); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 6b03eb5..c5691c5 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -80,7 +80,7 @@ csrrw t0,mscratch,x0 csrr s0,mstatus csrr t1,mepc - csrr t2,mbadaddr + csrr t2,mtval csrr t3,mcause STORE t0,2*REGBYTES(x2) STORE s0,32*REGBYTES(x2) -- To view, visit https://review.coreboot.org/c/coreboot/+/74569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8fa82b6131dec10f55e8ebcf36b34e30b57bad Gerrit-Change-Number: 74569 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/riscv: Fix compiler argument for clang
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74568 ) Change subject: arch/riscv: Fix compiler argument for clang ...................................................................... arch/riscv: Fix compiler argument for clang The suffixes zicsr and zifencei are assumed by default for clang. Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74568 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/riscv/Makefile.inc 1 file changed, 23 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index bbbdeb0..cc553c9 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -25,15 +25,21 @@ # suffixes in ARCH_SUFFIX_riscv. simple_riscv_flags = $(riscv_flags) +ifeq ($(CONFIG_COMPILER_GCC),y) +MARCH_SUFFIX=$(ARCH_SUFFIX_riscv) +else +MARCH_SUFFIX= +endif + ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) -riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) +riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) else riscv_flags += $(_rv_flags) simple_riscv_flags += $(_rv_flags) endif -riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) +riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name) -- To view, visit https://review.coreboot.org/c/coreboot/+/74568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75947f614c3600d5d9d461970159f0787fd6c3de Gerrit-Change-Number: 74568 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/myst: Add named GPIO's
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74593 ) Change subject: mb/google/myst: Add named GPIO's ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/74593/comment/ac304224_a9afc0d0 PS2, Line 30: #define LPC_RST_L_MB GPIO_32 > This is named `LPC_RST_L` in go/myst-gpios. LPC_RST_L is a macro defined by AMD for pin function and naming this the same way will conflict with that definition. -- To view, visit https://review.coreboot.org/c/coreboot/+/74593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed Gerrit-Change-Number: 74593 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 20:12:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Karthik Ramasubramanian (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 19:32:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74658/comment/cb323cc7_8f5ebab3 PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device : pointers were added right after the xhci_0 and xhci_1 controller device : pointers. > xhci2 would be bus C function 0, but that's not present on phoenix. […] pushed an update; please let me know if this is better now -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 19:24:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian. Hello Robert Zieba, build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74658 to look at the new patch set (#3). Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers Beware that there's no XHCI2 controller and the USB4 controller device pointers were added right after the xhci_0 and xhci_1 controller device pointers. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 --- M src/soc/amd/phoenix/include/soc/xhci.h 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74658/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74658/comment/0245a2d4_c3816076 PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device : pointers were added right after the xhci_0 and xhci_1 controller device : pointers. > The relevant code just doesn't support holes in the device list. […] xhci2 would be bus C function 0, but that's not present on phoenix. rembrandt (which mendocino is based on) has all three xhci0-2 and the two usb4 xhci controllers. i''l keep the defines as they are now, but add the comments -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 19:19:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable RTD3 root port mutex for WWAN
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73384 ) Change subject: mb/intel/mtlrvp: Enable RTD3 root port mutex for WWAN ...................................................................... mb/intel/mtlrvp: Enable RTD3 root port mutex for WWAN This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. The purpose of using this mutex is to prevent OSPM from calling _ON and _OFF methods while WWAN kernel driver is calling _RST, which accesses the GPIO pins. BUG=NA TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73384 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index e80c542..66f2179 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -297,6 +297,7 @@ register "srcclk_pin" = "1" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp7_rtd3 on end end chip drivers/wwan/fm -- To view, visit https://review.coreboot.org/c/coreboot/+/73384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058 Gerrit-Change-Number: 73384 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/adlrvp: Enable RTD3 root port mutex for WWAN
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73383 ) Change subject: mb/intel/adlrvp: Enable RTD3 root port mutex for WWAN ...................................................................... mb/intel/adlrvp: Enable RTD3 root port mutex for WWAN This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. The purpose of using this mutex is to prevent OSPM from calling _ON and _OFF methods while WWAN kernel driver is calling _RST, which accesses the GPIO pins. BUG=NA BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73383 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb 2 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index 544f9e2..fc4c11c 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -70,6 +70,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb index 544f9e2..fc4c11c 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb @@ -70,6 +70,7 @@ register "srcclk_pin" = "5" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" device generic 0 alias rp6_rtd3 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/73383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576 Gerrit-Change-Number: 73383 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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