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[M] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74607 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... mb/google/skyrim: Add named GPIO's Add named GPIO's to help prevent confusion in GPIO management BUG=b:278968729 TEST=TIMELESS=1 emerge-...coreboot before and after change compare binaries Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d --- M src/mainboard/google/skyrim/chromeos.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/skyrim/variants/baseboard/smihandler.c M src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c A src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h A src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/gpio.c A src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c A src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h A src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c M src/mainboard/google/skyrim/verstage.c 17 files changed, 132 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74607/1 diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c index c65e045..d020c09 100644 --- a/src/mainboard/google/skyrim/chromeos.c +++ b/src/mainboard/google/skyrim/chromeos.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <bootmode.h> -#include <gpio.h> +#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c index f265cbf..82d3ba9 100644 --- a/src/mainboard/google/skyrim/ec.c +++ b/src/mainboard/google/skyrim/ec.c @@ -4,9 +4,9 @@ #include <amdblocks/smi.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/smi.h> #include <variant/ec.h> +#include <variant/gpio.h> static const struct sci_source espi_sci_sources[] = { { diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 80839a0..7d0ab74 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_hotplug = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, - .gpio_group_id = GPIO_27, + .gpio_group_id = SD_AUX_RST_SOC_L, .clk_req = CLK_REQ1, }, { /* SSD */ @@ -50,7 +50,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h index c04cc5b..bc2f334 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -5,8 +5,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> -#include <gpio.h> +#include <variant/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ @@ -73,9 +72,6 @@ /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO -/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_84 - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h index eb17eff..24244cb 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h @@ -5,7 +5,73 @@ #include <gpio.h> +#define SOC_PWR_BTN_L GPIO_0 +#define SYS_RST_ODL GPIO_1 +#define SOC_PCIE_WAKE_L GPIO_2 +#define SOC_PEN_DETECT_ODL GPIO_3 +#define EN_PWR_FP GPIO_4 +#define EN_PP3300_TCHPAD GPIO_5 +#define SSD_AUX_RST_L GPIO_6 +#define WLAN_AUX_RST_L GPIO_7 +#define EN_PWR_WWAN_X GPIO_8 +#define EN_PP3300_WLAN GPIO_9 +#define BT_DISABLE GPIO_10 +#define EC_SOC_WAKE_ODL GPIO_11 +#define SOC_FP_RST_L GPIO_12 +#define USB_FAULT_R_ODL GPIO_16 +#define SOC_SAR_INT_R_L GPIO_17 +#define GSC_SOC_INT_L GPIO_18 +#define SOC_I2C_3_SCL GPIO_19 +#define SOC_I2C_3_SDA GPIO_20 +#define WLAN_DISABLE GPIO_21 +#define ESPI_EC_ALERT_SOC_R_ODL GPIO_22 +#define SOC_AC_PRES GPIO_23 +#define SOC_FP_INT_L GPIO_24 +#define SOC_PCIE_RST0_R_L GPIO_26 +#define SD_AUX_RST_SOC_L GPIO_27 +#define TCHSCR_INT_ODL GPIO_29 +#define ESPI_SOC_CS_EC_R_L GPIO_30 +#define LPC_RST_L_MB GPIO_32 +#define SOC_TCHPAD_INT_ODL GPIO_40 +#define WWAN_RST GPIO_42 +#define SOC_TDP_STRAP GPIO_67 +#define ESPI_SOC_D2_R GPIO_68 +#define ESPI_SOC_D3_R GPIO_69 +#define SOC_DISABLE_DISP_BL_R GPIO_74 +#define TCHSCR_REPORT_EN GPIO_76 +#define ESPI_SOC_CLK_R GPIO_77 +#define EN_PP3300_CAM GPIO_78 +#define ESPI_SOC_D1_R GPIO_80 +#define ESPI_SOC_D0_R GPIO_81 +#define EC_SOC_INT_ODL GPIO_84 +#define RAM_ID_1 GPIO_85 +#define RAM_ID_2 GPIO_89 +#define HP_INT_ODL GPIO_90 +#define RAM_ID_3 GPIO_91 +#define PCIE_0_SSD_CLKREQ_ODL GPIO_92 +#define SOC_I2C_2_SCL GPIO_113 +#define SOC_I2C_2_SDA GPIO_114 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define PCIE_2_WLAN_CLKREQ_ODL GPIO_116 +#define SOC_FPMCU_BOOT0 GPIO_130 +#define EN_PP3300_TCHSCR GPIO_131 +#define TCHSCR_RST_L GPIO_136 +#define SOC_BIOS_WP_L GPIO_138 +#define EN_SPKR GPIO_139 +#define UART_SOC_TX_FP_RX GPIO_140 +#define UART_DBG_TX_SOC_RX_R GPIO_141 +#define UART_FP_TX_SOC_RX GPIO_142 +#define UART_SOC_TX_DBG_RX_R GPIO_143 +#define RAM_ID_0 GPIO_144 +#define SOC_I2C_0_SCL GPIO_145 +#define SOC_I2C_0_SDA GPIO_146 +#define SOC_I2C_1_SCL GPIO_147 +#define SOC_I2C_1_SDA GPIO_148 + /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_138 +#define CROS_WP_GPIO SOC_BIOS_WP_L + +/* EC sync irq */ +#define EC_SYNC_IRQ EC_SOC_INT_ODL #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index e49b7c4..bb7c349 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <gpio.h> +#include <variant/gpio.h> #include <soc/pci_devs.h> #include <platform_descriptors.h> diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c index ff59b2b..a6aa1ba 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c +++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c @@ -6,8 +6,8 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> -#include <gpio.h> #include <variant/ec.h> +#include <variant/gpio.h> void mainboard_smi_sleep(u8 slp_typ) { diff --git a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c index 7e513ef..645fd6a 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <security/tpm/tis.h> -#include <gpio.h> +#include <variant/gpio.h> int tis_plat_irq_status(void) { - return gpio_interrupt_status(GPIO_18); + return gpio_interrupt_status(GSC_SOC_INT_L); } diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h new file mode 100644 index 0000000..eb7d1c4 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> + +/* EN_PWR_WWAN_X(GPIO_8) => CAM_PSW_L */ +#define CAM_PSW_L GPIO_8 + +/* SOC_SAR_INT_L(GPIO_17) => Unused */ +/* WWAN_RST(GPIO_42) => Unused */ diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c index 9753179..f1e1cbc 100644 --- a/src/mainboard/google/skyrim/variants/markarth/gpio.c +++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c @@ -5,18 +5,12 @@ /* GPIO configuration in ramstage */ static const struct soc_amd_gpio override_gpio_table[] = { - - /* SOC_PEN_DETECT_ODL => Unused */ + /* Unused GPIO's for this platform */ PAD_NC(GPIO_3), - /* EN_PWR_FP => Unused */ PAD_NC(GPIO_4), - /* EN_PWR_WWAN_X => Unused */ PAD_NC(GPIO_8), - /* SOC_FP_INT_L => Unused */ PAD_NC(GPIO_24), - /* SD_AUX_RST_SOC_L => Unused */ PAD_NC(GPIO_27), - /* WWAN_RST_L => Unused */ PAD_NC(GPIO_42), }; diff --git a/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h new file mode 100644 index 0000000..2daeaa1 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> + +/* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */ +/* EN_PWR_FP(GPIO_4) => Unused */ +/* EN_PWR_WWAN_X(GPIO_8) => Unused */ +/* SOC_FP_INT_L(GPIO_24) => Unused */ +/* SD_AUX_RST_SOC_L(GPIO_27) => Unused */ +/* WWAN_RST(GPIO_42) => Unused */ + +/* PCIE_1_SD_CLKREQ_ODL => PCIE_1_EMMC_CLKREQ_ODL */ +#define PCIE_1_EMMC_CLKREQ_ODL GPIO_115 diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 330fc46..9e2702f 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ1, }, }; @@ -69,7 +69,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c index 330fc46..9e2702f 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <variant/gpio.h> #include <baseboard/variants.h> #include <console/console.h> -#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -35,7 +35,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ1, }, }; @@ -69,7 +69,7 @@ .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, - .gpio_group_id = GPIO_6, + .gpio_group_id = SSD_AUX_RST_L, .clk_req = CLK_REQ0, }, }; diff --git a/src/mainboard/google/skyrim/verstage.c b/src/mainboard/google/skyrim/verstage.c index 1079e9b..8a9a2cc 100644 --- a/src/mainboard/google/skyrim/verstage.c +++ b/src/mainboard/google/skyrim/verstage.c @@ -3,11 +3,11 @@ #include <amdblocks/acpimmio.h> #include <arch/io.h> #include <baseboard/variants.h> -#include <gpio.h> #include <psp_verstage.h> #include <security/vboot/vboot_common.h> #include <soc/espi.h> #include <soc/southbridge.h> +#include <variant/gpio.h> void verstage_mainboard_early_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d Gerrit-Change-Number: 74607 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/google/myst: Rename baseboard gpios in gpio.c
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74593 to look at the new patch set (#3). Change subject: mb/google/myst: Rename baseboard gpios in gpio.c ...................................................................... mb/google/myst: Rename baseboard gpios in gpio.c Add named GPIO's to help prevent confusion in GPIO management BUG=b:278969100 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed --- M src/mainboard/google/myst/variants/baseboard/gpio.c 1 file changed, 101 insertions(+), 149 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74593/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed Gerrit-Change-Number: 74593 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/skyrim: rename baseboard gpios in gpio.c
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74592 to look at the new patch set (#3). Change subject: mb/google/skyrim: rename baseboard gpios in gpio.c ...................................................................... mb/google/skyrim: rename baseboard gpios in gpio.c Add named GPIO's to help prevent confusion in GPIO management BUG=b:278968729 TEST=builds Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/skyrim/variants/frostflow/gpio.c M src/mainboard/google/skyrim/variants/markarth/gpio.c M src/mainboard/google/skyrim/variants/winterhold/gpio.c 4 files changed, 111 insertions(+), 190 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/74592/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Gerrit-Change-Number: 74592 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Don't offer D3Cold when it's disabled
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74479 ) Change subject: soc/intel/meteorlake: Don't offer D3Cold when it's disabled ...................................................................... soc/intel/meteorlake: Don't offer D3Cold when it's disabled Use D3COLD_SUPPORT Kconfig option to adjust the maximum supported sleep state in ACPI. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/meteorlake/acpi/tcss.asl M src/soc/intel/meteorlake/acpi/tcss_dma.asl M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl M src/soc/intel/meteorlake/acpi/tcss_xhci.asl 4 files changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index c136048..1d562c9 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -657,6 +657,7 @@ } } +#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -763,6 +764,7 @@ STAT = 0 } } +#endif // D3COLD_SUPPORT /* * TCSS xHCI device diff --git a/src/soc/intel/meteorlake/acpi/tcss_dma.asl b/src/soc/intel/meteorlake/acpi/tcss_dma.asl index d00f794..94678fc 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_dma.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_dma.asl @@ -27,25 +27,45 @@ Method (_S0W, 0x0) { +#if CONFIG(D3COLD_SUPPORT) Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT } Method (_PR0) { +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT } Method (_PR3) { +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl index 48b8c73..6dbde46 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl @@ -247,25 +247,45 @@ Method (_S0W, 0x0, NotSerialized) { +#if CONFIG(D3COLD_SUPPORT) Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT } Method (_PR0) { +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT } Method (_PR3) { +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/meteorlake/acpi/tcss_xhci.asl b/src/soc/intel/meteorlake/acpi/tcss_xhci.asl index 422e6f7..ddc5a66 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_xhci.asl @@ -30,7 +30,11 @@ Method (_S0W, 0x0, NotSerialized) { +#if CONFIG(D3COLD_SUPPORT) Return (0x4) +#else + Return (0x3) +#endif // D3COLD_SUPPORT } /* @@ -39,6 +43,7 @@ */ Name (SD3C, 0) +#if CONFIG(D3COLD_SUPPORT) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -48,6 +53,7 @@ { Return (Package () { \_SB.PCI0.D3C }) } +#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method -- To view, visit https://review.coreboot.org/c/coreboot/+/74479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996 Gerrit-Change-Number: 74479 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/psp_verstage: Map/unmap boot device on need basis
by Karthik Ramasubramanian (Code Review) 21 Apr '23

21 Apr '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74606 ) Change subject: soc/amd/common/psp_verstage: Map/unmap boot device on need basis ...................................................................... soc/amd/common/psp_verstage: Map/unmap boot device on need basis Currently the SPI ROM is mapped completely when the boot device is initialized. That mapping remains active throughout the execution time of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB Slot in PSP for use during memory mapped or DMA access. With 16 MiB of mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total TLB slots is consumed. This leaves almost no scope for future expansion. With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out of TLB slots to support 32 MiB. Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN address during the boot device initialization. Update the boot device region operations to map and unmap the SPI flash with the desired offset and size using the SVC call. Then anytime a memory mapped SPI ROM access is performed: map the required area, read the data and immediately unmap the area. There is no update required when using CCP DMA, since the concerned SVC call performs mapping and unmapping of the required SPI flash area implicitly. With these changes, maximum of 8 slots(size of RO section) might get used at any point in time during the PSP verstage execution. BUG=b:240664755 TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and suspend/resume cycles for 50 iterations each. Ensured that there is no impact to boot time. Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/boot_dev.c M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 4 files changed, 90 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74606/1 diff --git a/src/soc/amd/common/psp_verstage/boot_dev.c b/src/soc/amd/common/psp_verstage/boot_dev.c index 4ee78b8..c1fd18a 100644 --- a/src/soc/amd/common/psp_verstage/boot_dev.c +++ b/src/soc/amd/common/psp_verstage/boot_dev.c @@ -11,22 +11,43 @@ #define DEST_BUF_ALIGNMENT 16 -static void *boot_dev_mmap(const struct region_device *rd, size_t offset, - size_t size __always_unused) +static void *boot_dev_mmap(const struct region_device *rd, size_t offset, size_t size) { const struct mem_region_device *mdev; + void *mapping = NULL; mdev = container_of(rd, __typeof__(*mdev), rdev); - return &(mdev->base[offset]); + if (mdev->base) { + if (svc_map_spi_rom(&mdev->base[offset], size, (void **)&mapping)) + printk(BIOS_ERR, "Error mapping SPI ROM to address.\n"); + } + + return mapping; } -static int boot_dev_munmap(const struct region_device *rd __always_unused, - void *mapping __always_unused) +static int boot_dev_munmap(const struct region_device *rd, void *mapping) { + uint32_t ret; + + if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) + printk(BIOS_ERR, "%s: Error %d unmapping %p\n", __func__, ret, mapping); return 0; } +static ssize_t boot_dev_mmap_readat(const struct region_device *rd, void *dest, + size_t offset, size_t size) +{ + void *mapping = boot_dev_mmap(rd, offset, size); + + if (!mapping) + return -1; + + memcpy(dest, mapping, size); + boot_dev_munmap(rd, mapping); + return size; +} + static ssize_t boot_dev_dma_readat(const struct region_device *rd, void *dest, size_t offset, size_t size) { @@ -38,8 +59,8 @@ memcpy_size = size; /* Alignment requirement is only on dest buffer for CCP DMA. So do a memcpy until the destination buffer alignment requirement is met. */ - if (memcpy_size) - memcpy(dest, &(mdev->base[offset]), memcpy_size); + if (memcpy_size && boot_dev_mmap_readat(rd, dest, offset, memcpy_size) != memcpy_size) + return -1; dest = ((char *)dest + memcpy_size); offset += memcpy_size; @@ -65,8 +86,7 @@ if (CONFIG(PSP_VERSTAGE_CCP_DMA)) return boot_dev_dma_readat(rd, dest, offset, size); - memcpy(dest, &(mdev->base[offset]), size); - return size; + return boot_dev_mmap_readat(rd, dest, offset, size); } const struct region_device_ops boot_dev_rdev_ro_ops = { diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index 7f850fd..0517545 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -90,19 +90,14 @@ {"AOAC", {FCH_IO_DEVICE_AOAC}, aoac_set_bar}, }; -uintptr_t *map_spi_rom(void) +void *map_spi_rom(void) { - uintptr_t *addr = NULL; struct spirom_info spi = {0}; if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); - if (spi.SpiBiosSmnBase != 0) - if (svc_map_spi_rom(spi.SpiBiosSmnBase, CONFIG_ROM_SIZE, (void **)&addr)) - printk(BIOS_DEBUG, "Error mapping SPI ROM to address.\n"); - - return addr; + return spi.SpiBiosSmnBase; } static uint32_t map_fch_devices(void) diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index c3240fa..eeb803f 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -38,7 +38,7 @@ #define POSTCODE_CMOS_RECOVERY 0xCA #define POSTCODE_EARLY_INIT_ERROR 0xCB #define POSTCODE_INIT_TPM_FAILED 0xCC - +#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 @@ -57,7 +57,7 @@ void verstage_soc_espi_init(void); void verstage_soc_i2c_init(void); void verstage_soc_spi_init(void); -uintptr_t *map_spi_rom(void); +void *map_spi_rom(void); uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset); uint32_t save_uapp_data(void *address, uint32_t size); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index e5b0277..9f10371 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -10,6 +10,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <fmap_config.h> #include <pc80/mc146818rtc.h> #include <soc/iomap.h> #include <soc/psp_transfer.h> @@ -74,7 +75,8 @@ const char *fname; const char *hash_fname; void *amdfw_location; - void *boot_dev_base = rdev_mmap_full(boot_device_ro()); + void *map_base = NULL; + size_t map_offset; /* Continue booting from RO */ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { @@ -85,36 +87,50 @@ if (vboot_is_firmware_slot_a(ctx)) { fname = "apu/amdfw_a"; hash_fname = "apu/amdfw_a_hash"; + map_offset = FMAP_SECTION_FW_MAIN_A_START - FMAP_SECTION_FLASH_START; + map_base = rdev_mmap(boot_device_ro(), map_offset, FMAP_SECTION_FW_MAIN_A_SIZE); } else { fname = "apu/amdfw_b"; hash_fname = "apu/amdfw_b_hash"; + map_offset = FMAP_SECTION_FW_MAIN_B_START - FMAP_SECTION_FLASH_START; + map_base = rdev_mmap(boot_device_ro(), map_offset, FMAP_SECTION_FW_MAIN_B_SIZE); + } + + if (!map_base) { + printk(BIOS_ERR, "Failed to map RW FW_MAIN section.\n"); + return POSTCODE_MAP_SPI_ROM_FAILED; } amdfw_location = cbfs_map(fname, NULL); if (!amdfw_location) { printk(BIOS_ERR, "AMD Firmware table not found.\n"); + rdev_munmap(boot_device_ro(), map_base); return POSTCODE_AMD_FW_MISSING; } + ef_table = (struct embedded_firmware *)amdfw_location; if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "ROMSIG address is not correct.\n"); + rdev_munmap(boot_device_ro(), map_base); return POSTCODE_ROMSIG_MISMATCH_ERROR; } psp_dir_addr = ef_table->new_psp_directory; bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + - (uint32_t)boot_dev_base); + (uint32_t)map_base - map_offset); if (*psp_dir_in_spi != PSP_COOKIE) { printk(BIOS_ERR, "PSP Directory address is not correct.\n"); + rdev_munmap(boot_device_ro(), map_base); return POSTCODE_PSP_COOKIE_MISMATCH_ERROR; } if (bios_dir_addr) { bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + - (uint32_t)boot_dev_base); + (uint32_t)map_base - map_offset); if (*bios_dir_in_spi != BHD_COOKIE) { printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); + rdev_munmap(boot_device_ro(), map_base); return POSTCODE_BHD_COOKIE_MISMATCH_ERROR; } } @@ -128,12 +144,14 @@ if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { printk(BIOS_ERR, "Updated BIOS Directory could not be set.\n"); + rdev_munmap(boot_device_ro(), map_base); return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; } if (CONFIG(SEPARATE_SIGNED_PSPFW)) update_psp_fw_hash_table(hash_fname); + rdev_munmap(boot_device_ro(), map_base); return 0; } @@ -208,7 +226,6 @@ { uint32_t retval; struct vb2_context *ctx = NULL; - void *boot_dev_base; uint32_t bootmode; /* @@ -324,14 +341,6 @@ if (retval) reboot_into_recovery(ctx, retval); - - post_code(POSTCODE_UNMAP_SPI_ROM); - boot_dev_base = rdev_mmap_full(boot_device_ro()); - if (boot_dev_base) { - if (svc_unmap_spi_rom((void *)boot_dev_base)) - printk(BIOS_ERR, "Error unmapping SPI rom\n"); - } - post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); -- To view, visit https://review.coreboot.org/c/coreboot/+/74606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2 Gerrit-Change-Number: 74606 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73257 to look at the new patch set (#3). Change subject: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache ...................................................................... soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 2 files changed, 31 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/73257/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Gerrit-Change-Number: 73257 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
by Arthur Heymans (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74659 ) Change subject: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318 Gerrit-Change-Number: 74659 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 21 Apr 2023 20:47:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache
by Fred Reitberger (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73257 to look at the new patch set (#2). Change subject: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache ...................................................................... soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 2 files changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/73257/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Gerrit-Change-Number: 73257 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/myst: Add named GPIO's
by Tim Van Patten (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Martin Roth, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74593 ) Change subject: mb/google/myst: Add named GPIO's ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/74593/comment/dc81d647_168f4e2a PS2, Line 30: #define LPC_RST_L_MB GPIO_32 > LPC_RST_L is a macro defined by AMD for pin function and naming this the same way will conflict with […] Please add a comment with the name in the spreadsheet, so it's easier to find in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/74593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed Gerrit-Change-Number: 74593 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 20:45:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable asynchronous End-Of-Post
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Subrata Banik. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74562 ) Change subject: mb/google/rex: Enable asynchronous End-Of-Post ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/74562/comment/90ef9090_d9e10b6c PS1, Line 92: if !BOARD_GOOGLE_REX_COMMON > Ack that looks a bit better to me; might be good to see if it's possible to have a soc-defined default and being able to select an override in the mainboard kconfig. since i'm not a maintainer of this subtree, i don't have a too strong opinion on this; just some suggestions about how i'd probably do this -- To view, visit https://review.coreboot.org/c/coreboot/+/74562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Gerrit-Change-Number: 74562 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 20:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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