coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/skyrim: Update GPIO names
by Jon Murphy (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74595 to look at the new patch set (#4). Change subject: mb/google/skyrim: Update GPIO names ...................................................................... mb/google/skyrim: Update GPIO names Update GPIO names in devicetree files to use the more descriptive versions in variant/gpio.h. This provides more clarity and insight into what GPIOs actually mean on the design. BUG=b:278968729 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I7443d1d1e3a2c00f2d2f76431f230a86faf551c6 --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb M src/mainboard/google/skyrim/variants/markarth/overridetree.cb M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 6 files changed, 70 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74595/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7443d1d1e3a2c00f2d2f76431f230a86faf551c6 Gerrit-Change-Number: 74595 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/myst: Add mainboard chip.h
by Jon Murphy (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Jon Murphy. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74670 to look at the new patch set (#2). Change subject: mb/google/myst: Add mainboard chip.h ...................................................................... mb/google/myst: Add mainboard chip.h Add mainboard chip.h to allow for using additional includes and specifically net names within the devicetree. BUG=b:278969100 TEST=builds Change-Id: I52be99c168ce0fd6f08258da443eeaebdfb78d0a Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/variants/baseboard/chip.h M src/mainboard/google/myst/variants/baseboard/devicetree.cb 3 files changed, 169 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74670/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52be99c168ce0fd6f08258da443eeaebdfb78d0a Gerrit-Change-Number: 74670 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/skyrim: Add mainboard chip.h
by Jon Murphy (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth. Hello build bot (Jenkins), Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74609 to look at the new patch set (#2). Change subject: mb/google/skyrim: Add mainboard chip.h ...................................................................... mb/google/skyrim: Add mainboard chip.h Add mainboard chip.h to allow for using additional includes and specifically net names within the devicetree. BUG=b:278968729 TEST=builds Change-Id: Ic609d294135e2982064cb1c1fe6eac98dc24086f --- M src/mainboard/google/skyrim/mainboard.c A src/mainboard/google/skyrim/variants/baseboard/chip.h M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 3 files changed, 274 insertions(+), 241 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74609/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic609d294135e2982064cb1c1fe6eac98dc24086f Gerrit-Change-Number: 74609 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/myst: Add mainboard chip.h
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74670 ) Change subject: mb/google/myst: Add mainboard chip.h ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/myst/variants/baseboard/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174766): https://review.coreboot.org/c/coreboot/+/74670/comment/6eb2c0eb_dd220ba3 PS1, Line 10: #endif adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/74670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52be99c168ce0fd6f08258da443eeaebdfb78d0a Gerrit-Change-Number: 74670 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 21:47:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/skyrim: Add mainboard chip.h
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74609 ) Change subject: mb/google/skyrim: Add mainboard chip.h ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174765): https://review.coreboot.org/c/coreboot/+/74609/comment/d560fb90_c5c9971a PS1, Line 10: #endif adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/74609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic609d294135e2982064cb1c1fe6eac98dc24086f Gerrit-Change-Number: 74609 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 21:47:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common: Update GPIO macros
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74591 ) Change subject: soc/amd/common: Update GPIO macros ...................................................................... Patch Set 2: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174760): https://review.coreboot.org/c/coreboot/+/74591/comment/6aca9eb4_ba3a55a2 PS2, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174760): https://review.coreboot.org/c/coreboot/+/74591/comment/49cc8855_e13adaf9 PS2, Line 11: to GPIO_NN names for use in their own development. Enabling projects to Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174760): https://review.coreboot.org/c/coreboot/+/74591/comment/1bed038c_5f942d9e PS2, Line 12: rename their own GPIOs to nets will hopefully make the code more readable Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I918d659eecf2076ed9089218177874ed2c9023b3 Gerrit-Change-Number: 74591 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 21:47:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/sconfig/main: Add variant/gpio.h to static.c
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Jon Murphy has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74594 ) Change subject: util/sconfig/main: Add variant/gpio.h to static.c ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia16211ef73fa9c6221f98c36879dd740631b8ad2 Gerrit-Change-Number: 74594 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: abandon

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[L] Change in coreboot[master]: mb/google/myst: Add mainboard chip.h
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74670 ) Change subject: mb/google/myst: Add mainboard chip.h ...................................................................... mb/google/myst: Add mainboard chip.h Add mainboard chip.h to allow for using additional includes and specifically net names within the devicetree. BUG=b:278969100 TEST=builds Change-Id: I52be99c168ce0fd6f08258da443eeaebdfb78d0a Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/variants/baseboard/chip.h M src/mainboard/google/myst/variants/baseboard/devicetree.cb 3 files changed, 169 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74670/1 diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index e433c98..457421b 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -7,6 +7,11 @@ #include <device/device.h> #include <variant/ec.h> +struct chip_operations mainboard_google_myst_variants_baseboard_ops = { + CHIP_NAME("Google Myst MB") + .enable_dev = NULL, +}; + static const struct fch_irq_routing fch_irq_map[] = { { 0, 0x00, 0x00 }, }; diff --git a/src/mainboard/google/myst/variants/baseboard/chip.h b/src/mainboard/google/myst/variants/baseboard/chip.h new file mode 100644 index 0000000..86825e5 --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/gpio.h> + +#ifndef MB_GOOGLE_MYST_CHIP_H +#define MB_GOOGLE_MYST_CHIP_H + +struct mainboard_google_myst_variants_baseboard_config {}; + +#endif \ No newline at end of file diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index fbc9e93..ba7d5ba 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,153 +1,156 @@ # SPDX-License-Identifier: GPL-2.0-or-later -chip soc/amd/phoenix - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | - GPIO_I2C2_SCL | GPIO_I2C3_SCL" +chip mainboard/google/myst/variants/baseboard + device domain 0 off end # dummy + chip soc/amd/phoenix + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # I2C Pad Control RX Select Configuration - register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad - register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen - register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC - register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB - # I2C Config - #+-------------------+----------------------------+ - #| Field | Value | - #+-------------------+----------------------------+ - #| I2C0 | Trackpad | - #| I2C1 | Touchscreen | - #| I2C2 | GSC TPM | - #| I2C3 | Speaker, Codec, P-SAR, USB | - #+-------------------+----------------------------+ - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - }" + # I2C Config + #+-------------------+----------------------------+ + #| Field | Value | + #+-------------------+----------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | GSC TPM | + #| I2C3 | Speaker, Codec, P-SAR, USB | + #+-------------------+----------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" - register "i2c[1]" = "{ - .speed = I2C_SPEED_FAST, - }" + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - .early_init = true, - }" + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - }" + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + }" - device domain 0 on - device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - device ref gfx on end # Internal GPU (GFX) - device ref xhci_0 on # USB 3.1 (USB0) - chip drivers/usb/acpi - device ref xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb3_port0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A1 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A1 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - device ref usb2_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port2 on end - end - chip drivers/usb/acpi - register "desc" = ""World-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port3 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)" - register "enable_delay_ms" = "500" - register "enable_off_delay_ms" = "200" - register "use_gpio_for_status" = "true" - device ref usb2_port4 on end + device domain 0 on + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""World-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(BT_DISABLE)" + register "enable_delay_ms" = "500" + register "enable_off_delay_ms" = "200" + register "use_gpio_for_status" = "true" + device ref usb2_port4 on end + end end end end end - end - device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - device ref usb4_xhci_0 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device ref usb4_xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb3_port6 on end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref usb4_xhci_0 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref usb4_xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port6 on end + end end - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb2_port6 on end + end + end + device ref usb4_xhci_1 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref usb4_xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB4 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port7 on end + end end end end end - device ref usb4_xhci_1 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device ref usb4_xhci_1_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB4 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" - device ref usb3_port7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" - device ref usb2_port7 on end - end - end + device ref iommu on end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 alias chrome_ec on end end end - end - device ref iommu on end - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 alias chrome_ec on end - end - end - end # domain - device ref uart_0 on end # UART0 - device ref i2c_0 on end - device ref i2c_1 on end - device ref i2c_2 on end - device ref i2c_3 on end -end # chip soc/amd/phoenix + end # domain + device ref uart_0 on end # UART0 + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + end # chip soc/amd/phoenix +end # chip mainboard/google/myst/variants/baseboard -- To view, visit https://review.coreboot.org/c/coreboot/+/74670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52be99c168ce0fd6f08258da443eeaebdfb78d0a Gerrit-Change-Number: 74670 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: mb/google/skyrim: Add mainboard chip.h
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74609 ) Change subject: mb/google/skyrim: Add mainboard chip.h ...................................................................... mb/google/skyrim: Add mainboard chip.h Add mainboard chip.h to allow for using additional includes and specifically net names within the devicetree. BUG=b:278968729 TEST=builds Change-Id: Ic609d294135e2982064cb1c1fe6eac98dc24086f --- M src/mainboard/google/skyrim/mainboard.c A src/mainboard/google/skyrim/variants/baseboard/chip.h M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 3 files changed, 244 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74609/1 diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 475e5cf..e7d0d6e 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -12,6 +12,11 @@ #include <soc/acpi.h> #include <variant/ec.h> +struct chip_operations mainboard_google_myst_variants_baseboard_ops = { + CHIP_NAME("Google Myst MB") + .enable_dev = NULL, +}; + /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is accessed via I/O ports 0xc00/0xc01. */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/chip.h b/src/mainboard/google/skyrim/variants/baseboard/chip.h new file mode 100644 index 0000000..86825e5 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/gpio.h> + +#ifndef MB_GOOGLE_MYST_CHIP_H +#define MB_GOOGLE_MYST_CHIP_H + +struct mainboard_google_myst_variants_baseboard_config {}; + +#endif \ No newline at end of file diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index f863197..2aec695 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -1,138 +1,188 @@ # SPDX-License-Identifier: GPL-2.0-or-later -chip soc/amd/mendocino - # eSPI Configuration - register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, - .generic_io_range[0] = { - .base = 0x62, - /* - * Only 0x62 and 0x66 are required. But, this is not supported by - * standard IO decodes and there are only 4 generic I/O windows - * available. Hence, open a window from 0x62-0x67. - */ - .size = 5, - }, - .generic_io_range[1] = { - .base = 0x800, /* EC_HOST_CMD_REGION0 */ - .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ - }, - .generic_io_range[2] = { - .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ - .size = 255, /* EC_MEMMAP_SIZE */ - }, - .generic_io_range[3] = { - .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ - .size = 8, /* 0x200 - 0x207 */ - }, +chip mainboard/google/skyrim/variants/baseboard + device domain 0 off end # dummy + chip soc/amd/mendocino - .io_mode = ESPI_IO_MODE_QUAD, - .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, - .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, - .periph_ch_en = 1, - .vw_ch_en = 1, - .oob_ch_en = 0, - .flash_ch_en = 0, + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), - }" + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, - register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | - GPIO_I2C2_SCL | GPIO_I2C3_SCL" + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), + }" - # I2C Pad Control RX Select Configuration - register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Touchpad - register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen - register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR - register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # I2C Config - #+-------------------+----------------------------+ - #| Field | Value | - #+-------------------+----------------------------+ - #| I2C0 | Trackpad | - #| I2C1 | Touchscreen | - #| I2C2 | Speaker, Codec, P-SAR, USB | - #| I2C3 | D2 TPM | - #+-------------------+----------------------------+ - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - }" + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Touchpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC - register "i2c[1]" = "{ - .speed = I2C_SPEED_FAST, - }" + # I2C Config + #+-------------------+----------------------------+ + #| Field | Value | + #+-------------------+----------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Speaker, Codec, P-SAR, USB | + #| I2C3 | D2 TPM | + #+-------------------+----------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" - register "i2c[2]" = "{ - .speed = I2C_SPEED_FAST, - }" + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .early_init = true, - }" + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" - # general purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" - register "gpp_clk_config[2]" = "GPP_CLK_REQ" - register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" - # PSPP doesn't save any power on this platform - register "pspp_policy" = "DXIO_PSPP_DISABLED" + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" - register "s0ix_enable" = "true" + # PSPP doesn't save any power on this platform + register "pspp_policy" = "DXIO_PSPP_DISABLED" - device domain 0 on - device ref lpc_bridge on - chip ec/google/chromeec - device pnp 0c09.0 alias chrome_ec on end + register "s0ix_enable" = "true" + + device domain 0 on + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 alias chrome_ec on end + end end - end - device ref gpp_bridge_0 on # WLAN - chip drivers/pcie/generic - register "wake_gpe" = "GEVENT_8" - register "wake_deepest" = "ACPI_S0" - register "name" = ""WLAN"" - device pci 00.0 on end + device ref gpp_bridge_0 on # WLAN + chip drivers/pcie/generic + register "wake_gpe" = "GEVENT_8" + register "wake_deepest" = "ACPI_S0" + register "name" = ""WLAN"" + device pci 00.0 on end + end end - end - device ref iommu on end - device ref gpp_bridge_1 on end # SD - device ref gpp_bridge_2 on - # Required so the NVMe gets placed into D3 when entering S0i3. - chip drivers/pcie/rtd3/device - register "name" = ""NVME"" - device pci 00.0 on end - end - end # NVMe + device ref iommu on end + device ref gpp_bridge_1 on end # SD + device ref gpp_bridge_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe - device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - device ref gfx on end # Internal GPU (GFX) - device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) - device ref crypto on end # Crypto Coprocessor - device ref xhci_0 on # USB 3.1 (USB0) - chip drivers/usb/acpi - device ref xhci_0_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb3_port0 on end + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port1 on end + end end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port0 on end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""World-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end end - chip drivers/usb/acpi - register "desc" = ""User-Facing Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port1 on end + end + end + device ref acp on end # Audio Processor (ACP) + device ref mp2 on end # Sensor Fusion Hub (MP2) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref xhci_2 on # USB 2.0 (USB2) + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_2_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(BT_DISABLE)" + register "enable_delay_ms" = "500" + register "enable_off_delay_ms" = "200" + register "use_gpio_for_status" = "true" + device usb 2.0 alias usb2_port5 on end + end end end end @@ -196,76 +246,55 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_18)" device i2c 50 alias ti50 on end end - end + chip drivers/acpi/thermal_zone + register "description" = ""Memory"" + use chrome_ec as temperature_controller + register "sensor_id" = "1" + register "polling_period" = "10" + register "critical_temperature" = "103" + register "passive_config.temperature" = "95" + register "use_acpi1_thermal_zone_scope" = "true" - # EC is configured to power off the system at 105C, so add a two degree - # buffer so the OS can gracefully shutdown. - # - # EC is configured to assert PROCHOT at 100C. That drastically lowers - # performance. Instead we will tell the OS to start throttling the CPUs - # at 95C in hopes that we don't hit the PROCHOT limit. - # - # We set use_acpi1_thermal_zone_scope because the Chrome ec.asl - # performs a `Notify` to the `_\TZ` scope. - chip drivers/acpi/thermal_zone - register "description" = ""Charger"" - use chrome_ec as temperature_controller - register "sensor_id" = "0" - register "polling_period" = "10" - register "critical_temperature" = "103" - register "passive_config.temperature" = "95" - register "use_acpi1_thermal_zone_scope" = "true" + device generic 1 on end + end + chip drivers/acpi/thermal_zone + register "description" = ""CPU"" + use chrome_ec as temperature_controller + register "sensor_id" = "2" + register "polling_period" = "10" + register "critical_temperature" = "103" + register "passive_config.temperature" = "95" + register "use_acpi1_thermal_zone_scope" = "true" - device generic 0 on end - end - chip drivers/acpi/thermal_zone - register "description" = ""Memory"" - use chrome_ec as temperature_controller - register "sensor_id" = "1" - register "polling_period" = "10" - register "critical_temperature" = "103" - register "passive_config.temperature" = "95" - register "use_acpi1_thermal_zone_scope" = "true" + device generic 2 on end + end + chip drivers/acpi/thermal_zone + register "description" = ""SOC"" + use chrome_ec as temperature_controller + register "sensor_id" = "3" + register "polling_period" = "10" + register "critical_temperature" = "103" + register "passive_config.temperature" = "95" + register "use_acpi1_thermal_zone_scope" = "true" - device generic 1 on end - end - chip drivers/acpi/thermal_zone - register "description" = ""CPU"" - use chrome_ec as temperature_controller - register "sensor_id" = "2" - register "polling_period" = "10" - register "critical_temperature" = "103" - register "passive_config.temperature" = "95" - register "use_acpi1_thermal_zone_scope" = "true" + device generic 3 on end + end - device generic 2 on end - end - chip drivers/acpi/thermal_zone - register "description" = ""SOC"" - use chrome_ec as temperature_controller - register "sensor_id" = "3" - register "polling_period" = "10" - register "critical_temperature" = "103" - register "passive_config.temperature" = "95" - register "use_acpi1_thermal_zone_scope" = "true" - - device generic 3 on end - end - - # DPTC: Refer the spec "FT6 Infrastructure Roadmap"#57316 - # Set system_configuration to 4 for 15W - register "system_configuration" = "4" - # Normal - register "slow_ppt_limit_mW" = "25000" - register "fast_ppt_limit_mW" = "30000" - register "slow_ppt_time_constant_s" = "5" - register "stapm_time_constant_s" = "275" - register "thermctl_limit_degreeC" = "100" - register "vrm_current_limit_mA" = "28000" - register "vrm_maximum_current_limit_mA" = "50000" - register "vrm_soc_current_limit_mA" = "10000" - # Throttle (e.g., Low/No Battery) - register "vrm_current_limit_throttle_mA" = "20000" - register "vrm_maximum_current_limit_throttle_mA" = "20000" - register "vrm_soc_current_limit_throttle_mA" = "10000" -end # chip soc/amd/mendocino + # DPTC: Refer the spec "FT6 Infrastructure Roadmap"#57316 + # Set system_configuration to 4 for 15W + register "system_configuration" = "4" + # Normal + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + # Throttle (e.g., Low/No Battery) + register "vrm_current_limit_throttle_mA" = "20000" + register "vrm_maximum_current_limit_throttle_mA" = "20000" + register "vrm_soc_current_limit_throttle_mA" = "10000" + end # chip soc/amd/mendocino +end # chip mainboard/google/skyrim/variants/baseboard \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/74609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic609d294135e2982064cb1c1fe6eac98dc24086f Gerrit-Change-Number: 74609 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/myst: Add named GPIO's
by Jon Murphy (Code Review) 21 Apr '23

21 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74608 ) Change subject: mb/google/myst: Add named GPIO's ...................................................................... mb/google/myst: Add named GPIO's Add named GPIO's to help prevent confusion in GPIO management BUG=b:278969100 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ie0ef4fa25e36f380af8eb432ee346e0022117d3c --- M src/mainboard/google/myst/chromeos.c M src/mainboard/google/myst/ec.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/myst/variants/myst/include/variant/gpio.h 6 files changed, 94 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74608/1 diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c index e488e81..5c10f65 100644 --- a/src/mainboard/google/myst/chromeos.c +++ b/src/mainboard/google/myst/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> void fill_lb_gpios(struct lb_gpios *gpios) {} diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/myst/ec.c index 060119d..d8c1ae3 100644 --- a/src/mainboard/google/myst/ec.c +++ b/src/mainboard/google/myst/ec.c @@ -3,9 +3,9 @@ #include <acpi/acpi.h> #include <amdblocks/smi.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/smi.h> #include <variant/ec.h> +#include <variant/gpio.h> static const struct sci_source espi_sci_sources[] = { { diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h index c6ab30f..2eeb167 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h @@ -5,8 +5,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> -#include <gpio.h> +#include <variant/gpio.h> #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ @@ -73,9 +72,6 @@ /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO -/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_90 - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h index a6683fd..13286b1 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h @@ -5,7 +5,78 @@ #include <gpio.h> +#define EC_SOC_PWR_BTN_ODL GPIO_0 +#define SYS_RST_ODL GPIO_1 +#define SOC_PCIE_WAKE_ODL GPIO_2 +#define EN_PWR_FP GPIO_4 +#define EN_PP3300_TCHPAD_X GPIO_5 +#define EN_PP3300_WWAN_X GPIO_6 +#define SOC_PEN_DETECT_ODL GPIO_7 +#define SOC_TCHPAD_INT_ODL GPIO_8 +#define EN_PP3300_WLAN_X GPIO_9 +#define WWAN_RST GPIO_11 +#define USB_FAULT_ODL GPIO_16 +#define EC_SOC_WAKE_R_ODL GPIO_17 +#define FP_SOC_INT_L GPIO_18 +#define I2C_SOC_AUDIO_HDMI_SCL_U GPIO_19 +#define I2C_SOC_AUDIO_HDMI_SDA_U GPIO_20 +#define ESPI_EC_ALERT_SOC_ODL GPIO_22 +#define SOC_AC_PRES_OD GPIO_23 +#define SOC_PCIE_RST0_R_L GPIO_26 +#define SOC_PCIE_RST1_R_L GPIO_27 +#define SD_AUX_RST GPIO_29 +#define ESPI_SOC_CS_EC_R_L GPIO_30 +#define SSD_AUX_RST GPIO_31 +#define LPC_RST_L_MB GPIO_32 +#define WLAN_AUX_RST_L GPIO_38 +#define WWAN_AUX_RST_L GPIO_39 +#define SOC_FP_RST_L GPIO_40 +#define SOC_MEM_VID_C1 GPIO_42 +#define ESPI_SOC_D2_EC_R GPIO_68 +#define ESPI_SOC_D3_EC_R GPIO_69 +#define SPI_SOC_CLK_FPMCU_R GPIO_70 +#define EN_TCHSCR_REPORT GPIO_74 +#define SPI_SOC_CS_FPMCU_R_L GPIO_75 +#define ESPI_SOC_CLK_EC_R GPIO_77 +#define RAM_ID_0 GPIO_78 +#define RAM_ID_1 GPIO_79 +#define ESPI_SOC_D1_EC_R GPIO_80 +#define ESPI_SOC_D0_EC_R GPIO_81 +#define GSC_SOC_INT_ODL GPIO_84 +#define HP_INT_ODL GPIO_89 +#define EC_SOC_INT_ODL GPIO_90 +#define TCHSCR_INT_ODL GPIO_91 +#define PCIE_0_WLAN_CLKREQ_ODL GPIO_92 +#define SPI_SOC_DO_FPMCU_DI_R GPIO_104 +#define SPI_SOC_DI_FPMCU_DO_R GPIO_105 +#define RAM_ID_2 GPIO_106 +#define RAM_ID_3 GPIO_107 +#define I2C_SOC_GSC_SCL_U GPIO_113 +#define I2C_SOC_GSC_SDA_U GPIO_114 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define PCIE_2_WWAN_CLKREQ_ODL GPIO_116 +#define PCIE_3_SSD_CLKREQ_ODL GPIO_131 +#define SOC_FP_BOOT0 GPIO_132 +#define EN_PP3300_CAM_X GPIO_135 +#define SOC_BIOS_WP_OD GPIO_139 +#define UART_SOC_TX_FPMCU_RX GPIO_140 +#define UART_SOC_RX_DBG_TX GPIO_141 +#define UART_SOC_RX_FPMCU_TX GPIO_142 +#define UART_SOC_TX_DBG_RX GPIO_143 +#define EN_PP3300_TCHSCR_X GPIO_144 +#define I2C_SOC_TCHPAD_SCL GPIO_145 +#define I2C_SOC_TCHPAD_SDA GPIO_146 +#define I2C_SOC_TCHSCR_SCL GPIO_147 +#define I2C_SOC_TCHSCR_SDA GPIO_148 +#define EN_SPKR GPIO_153 +#define BT_DISABLE GPIO_154 +#define WLAN_DISABLE GPIO_156 +#define TCHSCR_RST_L GPIO_157 + +/* EC sync irq */ +#define EC_SYNC_IRQ EC_SOC_INT_ODL + /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_139 +#define CROS_WP_GPIO SOC_BIOS_WP_OD #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 3f69548..a15a819 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <gpio.h> +#include <variant/gpio.h> /* This function provides base GPIO configuration table. */ diff --git a/src/mainboard/google/myst/variants/myst/include/variant/gpio.h b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/74608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ef4fa25e36f380af8eb432ee346e0022117d3c Gerrit-Change-Number: 74608 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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