coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
by Martin Roth (Code Review) 21 Apr '23

21 Apr '23

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74583 ) Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead ...................................................................... mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:278495684 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74583 Reviewed-by: Chao Gui <chaogui(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c 1 file changed, 29 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved Chao Gui: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c index 330fc46..94eb465 100644 --- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -74,7 +74,7 @@ }, }; -#define NVME_CLKREQ_GPIO 92 +#define EMMC_CLKREQ_GPIO 115 void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) { /* @@ -85,13 +85,13 @@ * This allows checking the state of the NVMe device clkreq signal and enabling * either eMMC or NVMe based on that. */ - if (gpio_get(NVME_CLKREQ_GPIO)) { - printk(BIOS_DEBUG, "Enabling eMMC.\n"); - *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); - *dxio_descs = emmc_dxio_descriptors; - } else { + if (gpio_get(EMMC_CLKREQ_GPIO)) { printk(BIOS_DEBUG, "Enabling NVMe.\n"); *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); *dxio_descs = nvme_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Gerrit-Change-Number: 74583 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: [RFC] drivers/option: Add option list in cbtable
by Benjamin Doron (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Angel Pons, Maximilian Brune. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74121 ) Change subject: [RFC] drivers/option: Add option list in cbtable ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Looking at EDK2's UefiInternalFormRespresentation header, I had some ideas: - Should we have per-option help text? - Currently, I mark all options as RESET_REQUIRED. If it's likely some options won't require a reset to apply, can we add a flag? - Please add an `OPTION_TEXT`, so we can notify the user. For instance, boards might display "EEPROM corrupted, contact manufacturer" - When we think about dependencies between options, we should consider logical relationships - `suppressif X AND NOT Y` - Since there is also OR, maybe tag these and we'll process them in order - if necessary, we can provide a field(s) for equality operators. Another thing to consider behaviour if the dependencies fail - suppress, grayout or allow the behaviour to be determined? The last one adds more complexity. There's a lot more that's possible, such as arithmetic, bitwise logic and shifts, 'casting' type operators (including string `TO_LOWER` and `TO_UPPER`), but these get harder to justify and I'd rather neither of us implement the entire IFR language -- To view, visit https://review.coreboot.org/c/coreboot/+/74121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:54:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/mainboard/hp: Add more about internal flashing
by Václav Straka (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Felix Singer, Václav Straka. Hello Felix Singer, build bot (Jenkins), Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74248 to look at the new patch set (#10). Change subject: Documentation/mainboard/hp: Add more about internal flashing ...................................................................... Documentation/mainboard/hp: Add more about internal flashing Add a more detailed explanation of internal flashing on the HP Compaq 8200 Elite SFF. Signed-off-by: Václav Straka <venda.straka(a)gmail.com> Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 --- M Documentation/mainboard/hp/compaq_8200_sff.md A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg 2 files changed, 102 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/74248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 Gerrit-Change-Number: 74248 Gerrit-PatchSet: 10 Gerrit-Owner: Václav Straka Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Václav Straka Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74618 ) Change subject: nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include ...................................................................... nb/amd/pi/00730F01/northbridge: remove unneeded AGESA.h include TEST=Timeless build for pcengines/apu2 results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If95eb9e5135de2b256d1f584afcedfd6e0cf8d8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74618 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d373493..cba57d8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -15,7 +15,6 @@ #include <lib.h> #include <cpu/x86/mp.h> #include <Porting.h> -#include <AGESA.h> #include <Topology.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/74618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95eb9e5135de2b256d1f584afcedfd6e0cf8d8e Gerrit-Change-Number: 74618 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Karthik Ramasubramanian (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 40: (4 comments) Patchset: PS40: Sorry for the last minute comment. File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/38416744_9d195be5 PS40, Line 10: PCIE_ENGINE Based on schematics, we dont have PCIe based WWAN at the moment. The concerned physical lane is attached to a Trace Point. I am waiting for EE team to confirm the plan. Since it is not used, enabling it may just add to the link training time and hence boot time. Felix, can you please confirm if my understanding is correct. If so, we can mark this engine as UNUSED_ENGINE. https://review.coreboot.org/c/coreboot/+/74112/comment/55c77640_c9ce078b PS40, Line 41: GPIO_29 Can be removed. This GPIO is passed by coreboot to FSP to SMU so that SMU can save and restore this GPIO during S0i3. This GPIO is in S5 domain and its state does not get reset on S0i3. Hence it does not have to be saved/restored during S0i3 by SMU. Usually we do this for GPIOs in S0 domain which loses state during S0i3. https://review.coreboot.org/c/coreboot/+/74112/comment/799ca0b8_79b48f04 PS40, Line 53: GPIO_31 Same comment as above. -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 40 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:51:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: replace some magic numbers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74617 ) Change subject: cpu/amd/pi/00730F01/fixme: replace some magic numbers ...................................................................... cpu/amd/pi/00730F01/fixme: replace some magic numbers TEST=Timeless build for pcengines/apu2 results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/74617 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/cpu/amd/pi/00730F01/fixme.c 1 file changed, 21 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index d36f507..9724133 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -3,6 +3,7 @@ #include <amdblocks/pci_devs.h> #include <arch/hpet.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -16,13 +17,14 @@ * set to non-posted regions. Last address before processor local APIC * at FEE00000, set NP (non-posted) bit. */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7)); + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, + ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8 | (1 << 7)); /* lowest NP address is HPET at FED00000 */ pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last - address before non-posted range */ - pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00); + /* Map the remaining PCI hole as posted MMIO. */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, + ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); /* Send all IO (0000-FFFF) to southbridge. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96f4655a3b4dc621ef77c4d97d2927565d634ec Gerrit-Change-Number: 74617 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions Use coreboot's native PCI access functions instead of using the vendorcode's PCI access functions to set up the CPU IO routing in function 1 of the HT PCI device. This file still has room for improvement, but at least it's now using coreboot-native functionality. Stoneyridge has a nicer implementation, but looking into possibly unifying those is out of scope for this patch. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/cpu/amd/pi/00730F01/fixme.c 1 file changed, 35 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index bc649b7..d36f507 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,54 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/pci_devs.h> #include <arch/hpet.h> #include <cpu/amd/mtrr.h> +#include <device/pci.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> void amd_initcpuio(void) { - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0xf4, 1); /* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. + * set to non-posted regions. Last address before processor local APIC + * at FEE00000, set NP (non-posted) bit. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; - /* set NP (non-posted) bit */ - PciData |= 1 << 7; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + pci_write_config32(_SOC_DEV(0x18, 1), 0x84, 0x00fedf00 | (1 << 7)); /* lowest NP address is HPET at FED00000 */ - PciData = (HPET_BASE_ADDRESS >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0x80, (HPET_BASE_ADDRESS >> 8) | 3); - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Map the remaining PCI hole as posted MMIO. 0xfecf0000 is the last + address before non-posted range */ + pci_write_config32(_SOC_DEV(0x18, 1), 0x8c, 0x00fecf00); + pci_write_config32(_SOC_DEV(0x18, 1), 0x88, (get_top_of_mem_below_4gb() >> 8) | 3); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_write_config32(_SOC_DEV(0x18, 1), 0xc4, 0x0000f000); + pci_write_config32(_SOC_DEV(0x18, 1), 0xc0, 0x00000003); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Mark Hasemeyer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Tim Van Patten. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 40: (1 comment) File src/mainboard/google/myst/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74112/comment/d6fa4b8b_57be1ff4 PS40, Line 41: .gpio_group_id = GPIO_29, GPIOs should be named pending: https://review.coreboot.org/c/coreboot/+/74593 -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 40 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74616 ) Change subject: cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions ...................................................................... Patch Set 1: (1 comment) File src/cpu/amd/pi/00730F01/fixme.c: https://review.coreboot.org/c/coreboot/+/74616/comment/dd4ea410_03f816e7 PS1, Line 19: 0x00fedf00 > Nevermind, it looks like we're good. no, that magic constant is what gets written to the register. address bits 0..15 aren't taken into account here and the lower 8 bits in the register aren't address bits, but some control bits. this patch only changed the regster accesses, but preserved the magic constants (although making them use lower-case chars). the next one will get rid of some of the magic constants; the replacements were inspired by the stoneyridge code -- To view, visit https://review.coreboot.org/c/coreboot/+/74616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c Gerrit-Change-Number: 74616 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:44:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Mark Hasemeyer (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Nien, Jon Murphy, Martin Roth, Tim Van Patten. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74592 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74592/comment/c6e545b4_879b5f1a PS2, Line 38: .gpio_group_id = SSD_AUX_RST_L, SD_AUX_RST_SOC_L File src/mainboard/google/skyrim/variants/markarth/gpio.c: https://review.coreboot.org/c/coreboot/+/74592/comment/9bf73a92_94f111bc PS2, Line 10: PAD_NC(GPIO_3), I know these are not named b/c they are not used, but it feels like another place in code we could forget to update values if pins move around (b/c of rework or new proto, etc). I could see us updating the value of `SOC_PEN_DETECT_ODL` and forget to change it here. -- To view, visit https://review.coreboot.org/c/coreboot/+/74592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340 Gerrit-Change-Number: 74592 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 15:42:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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