coreboot-gerrit April 2023

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[L] Change in coreboot[master]: sb,soc/intel/common: Add common get_pmbase()
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70048 to look at the new patch set (#10). Change subject: sb,soc/intel/common: Add common get_pmbase() ...................................................................... sb,soc/intel/common: Add common get_pmbase() Also get pch_log_state() from pmutil.h, redundant declaration caused build to fail. Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/include/soc/iomap.h M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 63 files changed, 150 insertions(+), 153 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70048/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/70048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Gerrit-Change-Number: 70048 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74657 to look at the new patch set (#3). Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 --- M src/soc/amd/phoenix/xhci.c 1 file changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74657/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74658 ) Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers ...................................................................... soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers Beware that there's no XHCI2 controller and the USB4 controller device pointers were added right after the xhci_0 and xhci_1 controller device pointers. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 --- M src/soc/amd/phoenix/include/soc/xhci.h 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74658/1 diff --git a/src/soc/amd/phoenix/include/soc/xhci.h b/src/soc/amd/phoenix/include/soc/xhci.h index ec71ece..870228e 100644 --- a/src/soc/amd/phoenix/include/soc/xhci.h +++ b/src/soc/amd/phoenix/include/soc/xhci.h @@ -7,8 +7,8 @@ #define SOC_XHCI_0 DEV_PTR(xhci_0) #define SOC_XHCI_1 DEV_PTR(xhci_1) -#define SOC_XHCI_2 NULL -#define SOC_XHCI_3 NULL +#define SOC_XHCI_2 DEV_PTR(usb4_xhci_0) +#define SOC_XHCI_3 DEV_PTR(usb4_xhci_1) #define SOC_XHCI_4 NULL #define SOC_XHCI_5 NULL #define SOC_XHCI_6 NULL -- To view, visit https://review.coreboot.org/c/coreboot/+/74658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14725d4b546ffcca42e21bbe7756babaaff8fea3 Gerrit-Change-Number: 74658 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74657 to look at the new patch set (#2). Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 --- M src/soc/amd/phoenix/xhci.c 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74657/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix: Update XHCI events
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74280 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/phoenix: Update XHCI events ...................................................................... soc/amd/phoenix: Update XHCI events Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI to allow for XHCI events to be logged. BUG=b:277273428 TEST=builds Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74280 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/Kconfig A src/soc/amd/phoenix/include/soc/xhci.h M src/soc/amd/phoenix/xhci.c 3 files changed, 41 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 5d3adec..64617f9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -74,6 +74,7 @@ select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_BLOCK_XHCI select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct diff --git a/src/soc/amd/phoenix/include/soc/xhci.h b/src/soc/amd/phoenix/include/soc/xhci.h new file mode 100644 index 0000000..ec71ece --- /dev/null +++ b/src/soc/amd/phoenix/include/soc/xhci.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PHOENIX_XHCI_H +#define AMD_PHOENIX_XHCI_H + +#include <device/device.h> + +#define SOC_XHCI_0 DEV_PTR(xhci_0) +#define SOC_XHCI_1 DEV_PTR(xhci_1) +#define SOC_XHCI_2 NULL +#define SOC_XHCI_3 NULL +#define SOC_XHCI_4 NULL +#define SOC_XHCI_5 NULL +#define SOC_XHCI_6 NULL +#define SOC_XHCI_7 NULL + +#endif /* AMD_PHOENIX_XHCI_H */ diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 06481ed..8bb446f 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -4,6 +4,7 @@ #include <amdblocks/gpio.h> #include <amdblocks/smi.h> +#include <amdblocks/xhci.h> #include <bootstate.h> #include <device/device.h> #include <device/pci_ids.h> @@ -14,13 +15,13 @@ static const struct sci_source xhci_sci_sources[] = { { .scimap = SMITYPE_XHC0_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG }, { .scimap = SMITYPE_XHC1_PME, - .gpe = GEVENT_31, + .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG } -- To view, visit https://review.coreboot.org/c/coreboot/+/74280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Gerrit-Change-Number: 74280 Gerrit-PatchSet: 17 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix: Update XHCI events
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Jon Murphy, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74280 ) Change subject: soc/amd/phoenix: Update XHCI events ...................................................................... Patch Set 16: (1 comment) File src/soc/amd/phoenix/xhci.c: https://review.coreboot.org/c/coreboot/+/74280/comment/cc434ab5_3870b614 PS13, Line 3: /* TODO: Update for Phoenix */ > pushed a patch train ending with CB:74657 […] i'll submit this one out of order and rebase my patch on top of this, so that it can use XHCI_GEVENT -- To view, visit https://review.coreboot.org/c/coreboot/+/74280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Gerrit-Change-Number: 74280 Gerrit-PatchSet: 16 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 14:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Update XHCI events
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Jon Murphy, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74280 ) Change subject: soc/amd/phoenix: Update XHCI events ...................................................................... Patch Set 16: (1 comment) File src/soc/amd/phoenix/xhci.c: https://review.coreboot.org/c/coreboot/+/74280/comment/f9b15d61_ed2bc4d4 PS13, Line 3: /* TODO: Update for Phoenix */ > Not for this change. […] pushed a patch train ending with CB:74657 i'm pretty sure that last time i looked, those bits weren't in the ppr -- To view, visit https://review.coreboot.org/c/coreboot/+/74280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922 Gerrit-Change-Number: 74280 Gerrit-PatchSet: 16 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 14:19:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74657 ) Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 --- M src/soc/amd/phoenix/xhci.c 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74657/1 diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 06481ed..6f97b32 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -23,6 +23,18 @@ .gpe = GEVENT_31, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC3_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG } }; @@ -44,6 +56,16 @@ } } + if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { + *gpe = xhci_sci_sources[2].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; + } + } + return CB_ERR_ARG; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74656 ) Change subject: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN ...................................................................... soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the internal PCI buses. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 --- M src/soc/amd/cezanne/include/soc/pci_devs.h M src/soc/amd/glinda/include/soc/pci_devs.h M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/include/soc/pci_devs.h M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/include/soc/pci_devs.h 6 files changed, 20 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74656/1 diff --git a/src/soc/amd/cezanne/include/soc/pci_devs.h b/src/soc/amd/cezanne/include/soc/pci_devs.h index 8f5793b..2337e0c 100644 --- a/src/soc/amd/cezanne/include/soc/pci_devs.h +++ b/src/soc/amd/cezanne/include/soc/pci_devs.h @@ -108,7 +108,7 @@ #define SATA1_DEVFN PCI_DEVFN(SATA1_DEV, SATA1_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) /* SMBUS */ diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index 4e0bf9d..a37d3ee 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -86,7 +86,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index 78ca94f..dad5593 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -48,7 +48,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/mendocino/include/soc/pci_devs.h b/src/soc/amd/mendocino/include/soc/pci_devs.h index 14c8300..2c81a5b 100644 --- a/src/soc/amd/mendocino/include/soc/pci_devs.h +++ b/src/soc/amd/mendocino/include/soc/pci_devs.h @@ -84,7 +84,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index 720cc76..e564991 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -49,7 +49,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/phoenix/include/soc/pci_devs.h b/src/soc/amd/phoenix/include/soc/pci_devs.h index 0dde0ba..cd7ad08 100644 --- a/src/soc/amd/phoenix/include/soc/pci_devs.h +++ b/src/soc/amd/phoenix/include/soc/pci_devs.h @@ -104,7 +104,7 @@ #define GFX_IPU_DEVFN PCI_DEVFN(GFX_IPU_DEV, GFX_IPU_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define USB4_XHCI0_DEV 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Gerrit-Change-Number: 74656 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
by Felix Held (Code Review) 21 Apr '23

21 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74655 ) Change subject: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 ...................................................................... soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 In the PPRs #57019 Rev 3.03 and #57396 Rev 3.04, SMITYPE_XHC3_PME, SMITYPE_XHC4_PME and SMITYPE_CUR_TEMP_STATUS_5 are defined, so add those defines. When doing the initial update for Phoenix, at least XHC3 and XHC4 PME events were missing from the PPR. Those two are the PME events of the two USB4 controllers. SMITYPE_XHC2_PME doesn't exist on this SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 --- M src/soc/amd/phoenix/include/soc/smi.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74655/1 diff --git a/src/soc/amd/phoenix/include/soc/smi.h b/src/soc/amd/phoenix/include/soc/smi.h index 034a327..e99b172 100644 --- a/src/soc/amd/phoenix/include/soc/smi.h +++ b/src/soc/amd/phoenix/include/soc/smi.h @@ -102,7 +102,10 @@ #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-63 Reserved */ +/* 59-60 Reserved */ +#define SMITYPE_XHC3_PME 61 +#define SMITYPE_XHC4_PME 62 +#define SMITYPE_CUR_TEMP_STATUS_5 63 #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -- To view, visit https://review.coreboot.org/c/coreboot/+/74655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Gerrit-Change-Number: 74655 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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