coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust USB settings
by Paul Menzel (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74651 ) Change subject: mb/siemens/mc_ehl4: Adjust USB settings ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Gerrit-Change-Number: 74651 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 12:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
by Paul Menzel (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74650 ) Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74650/comment/04de88ef_29cfe3ac PS2, Line 10: Kconfig … copy-pasted Kconfig switch …? -- To view, visit https://review.coreboot.org/c/coreboot/+/74650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Gerrit-Change-Number: 74650 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 12:01:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Disable PCIe device I2C4
by Paul Menzel (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74629 ) Change subject: mb/siemens/mc_ehl4: Disable PCIe device I2C4 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74629/comment/201fd0ac_f37759b9 PS2, Line 9: the device can be removed … remove the device… -- To view, visit https://review.coreboot.org/c/coreboot/+/74629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a5d1d27a57508d70bf30cf8e71aa1ee33bcbf13 Gerrit-Change-Number: 74629 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 12:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust GPIOs
by Paul Menzel (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74628 ) Change subject: mb/siemens/mc_ehl4: Adjust GPIOs ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74628/comment/010a98ae_b359a40a PS2, Line 9: Set the GPIOs according to the circuit diagram for this mainboard. For me it’s unclear, if the GPIO configuration was copy-pasted before, and therefore was wrong or not. It’d be great, if you made that clear. File src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c: https://review.coreboot.org/c/coreboot/+/74628/comment/9ac3fd4e_9600d4ed PS2, Line 8: Unrelated? -- To view, visit https://review.coreboot.org/c/coreboot/+/74628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Gerrit-Change-Number: 74628 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 12:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74353 to look at the new patch set (#2). Change subject: asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC For uni-processor platforms, with SMP=n or MAX_CPUS=1, neither the LAPIC or IOAPIC MADT entries are added. Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig D src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/southbridge/intel/i82371eb/Kconfig 3 files changed, 16 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/74353/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361 Gerrit-Change-Number: 74353 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/ibm/power9/*: add file structure for SOC
by Maciej Pijanowski (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Michał Żygowski, Michał Kopeć, Krystian Hebel, Sergii Dmytruk. Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67062 ) Change subject: soc/ibm/power9/*: add file structure for SOC ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67062/comment/afabaf21_ed4d928d PS3, Line 10: Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Sergii, can you please add here Igor instead (as an author), and yourself (as a commiter)? Krystian, please confirm that you are ok with that, if you were not original author here. -- To view, visit https://review.coreboot.org/c/coreboot/+/67062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3 Gerrit-Change-Number: 67062 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 21 Apr 2023 11:26:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Nico Huber, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74441 ) Change subject: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... Patch Set 3: (1 comment) File src/cpu/intel/speedstep/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174710): https://review.coreboot.org/c/coreboot/+/74441/comment/f1e19e85_aeb94020 PS3, Line 108: #if 0 Consider removing the code enclosed by this #if 0 and its #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 21 Apr 2023 10:54:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ACPI: Make FADT entries for RTC/CMOS architectural
by build bot (Jenkins) (Code Review) 21 Apr '23

21 Apr '23

1 0

[M] Change in coreboot[master]: ACPI: Make FADT entries for RTC/CMOS architectural
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Fred Reitberger, Tim Chu, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74601 ) Change subject: ACPI: Make FADT entries for RTC/CMOS architectural ...................................................................... ACPI: Make FADT entries for RTC/CMOS architectural For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/arch/x86/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 28 files changed, 32 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74601/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 601e581..0fb0f18 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1748,9 +1748,6 @@ fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); - if (CONFIG(USE_PC_CMOS_ALTCENTURY)) - fadt->century = RTC_CLK_ALTCENTURY; - fadt->sci_int = acpi_sci_int(); arch_fill_fadt(fadt); diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index e1ef978..7f3edf4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -24,4 +24,19 @@ fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } + +#define RTC_DATE_ALARM 0xd +#define RTC_CLK_ALTCENTURY 0x32 + +/* unused, from soc/amd */ +#define RTC_CENTURY 0x48 + + if (CONFIG(PC80_SYSTEM)) { + fadt->day_alrm = RTC_DATE_ALARM; + fadt->mon_alrm = 0x0; /* not supported */ + } + + /* Careful with USE_OPTION_TABLE. */ + if (CONFIG(USE_PC_CMOS_ALTCENTURY)) + fadt->century = RTC_CLK_ALTCENTURY; } diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 11f73e4..912aee1 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -61,8 +61,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h index ab90c96..1a0e2a1 100644 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -10,11 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 2c21801..5304ac5 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -64,8 +64,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/glinda/include/soc/acpi.h b/src/soc/amd/glinda/include/soc/acpi.h index 69e2f87..138086e 100644 --- a/src/soc/amd/glinda/include/soc/acpi.h +++ b/src/soc/amd/glinda/include/soc/acpi.h @@ -12,11 +12,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 907bc53..8627c69 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -63,8 +63,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/mendocino/include/soc/acpi.h b/src/soc/amd/mendocino/include/soc/acpi.h index 45e8a1b..ac3c490 100644 --- a/src/soc/amd/mendocino/include/soc/acpi.h +++ b/src/soc/amd/mendocino/include/soc/acpi.h @@ -10,11 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index cd22934..aa88f26 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -64,8 +64,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/phoenix/include/soc/acpi.h b/src/soc/amd/phoenix/include/soc/acpi.h index dc09a1d..823b9ce8 100644 --- a/src/soc/amd/phoenix/include/soc/acpi.h +++ b/src/soc/amd/phoenix/include/soc/acpi.h @@ -12,11 +12,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 26c2bc9..40f687f 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -70,7 +70,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 741b732..3b83123 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -10,9 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 2edb5c0..ccf05de 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -66,7 +66,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 302416e..0065d6e 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -14,9 +14,6 @@ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) #endif -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d - const char *soc_acpi_name(const struct device *dev); #endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 8a2831b..18ae68b 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -22,8 +22,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 526f797..b3cbd7e 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -23,8 +23,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 9a4c036..f67ab37 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -22,8 +22,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 32; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0c85c2e..7ba80b9 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -106,7 +106,6 @@ /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 39dbd4a..fc00dcb 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -47,8 +47,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - /* RTC Registers */ - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; /* PM2 Control Registers */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 1080b6c..134c87b 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -39,8 +39,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index e76682d..b0d719f 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -25,8 +25,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index fafbdcf..3728f8f 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -32,8 +32,7 @@ fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ - fadt->mon_alrm = 0x0; /* not supported */ + /* * bit meaning * 0 1: We have user-visible legacy devices diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index e5ad336..56c3cc7 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -19,8 +19,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 57ff9ab..e4a2c29 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -34,8 +34,7 @@ fadt->duty_width = 3; else fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 1409d18..4c3e51f 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -27,8 +27,7 @@ fadt->p_lvl3_lat = 0x39; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 0e4dd76..2184d54 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -27,8 +27,7 @@ fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */ fadt->duty_offset = 1; fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index d750890..44ee59a 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -25,8 +25,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index eaea091..d83c58f 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -37,8 +37,6 @@ else fadt->gpe0_blk_len = 2 * 8; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | -- To view, visit https://review.coreboot.org/c/coreboot/+/74601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Gerrit-Change-Number: 74601 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: ACPI: Make FADT entries for SMI architectural
by Kyösti Mälkki (Code Review) 21 Apr '23

21 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74600 ) Change subject: ACPI: Make FADT entries for SMI architectural ...................................................................... ACPI: Make FADT entries for SMI architectural Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 20 files changed, 17 insertions(+), 98 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74600/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 0ff0ded..e1ef978 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <cf9_reset.h> +#include <cpu/x86/smm.h> void arch_fill_fadt(acpi_fadt_t *fadt) { @@ -17,4 +18,10 @@ fadt->flags |= ACPI_FADT_RESET_REGISTER; } + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } } diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 7a64c11..11f73e4 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -49,12 +49,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index d97dc09..2c21801 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -52,12 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 94cb246..907bc53 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -51,12 +51,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 427fb74..cd22934 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -52,12 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 1c40ab7..26c2bc9 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -57,11 +57,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index febe0c8..2edb5c0 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -51,11 +51,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index c01a79a..8a2831b 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -10,11 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index d071b92..526f797 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,11 +11,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 2ffebc3..9a4c036 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -10,11 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 1b5538f..0c85c2e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -94,11 +94,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 9a1c5de..1080b6c 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -26,11 +26,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = ACPI_SMI_CTL_PORT; - fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; - fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index 31f2a06..e76682d 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index bb13ed7..fafbdcf 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -17,10 +17,6 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - if (permanent_smi_handler()) { - /* TODO: SMI handler is not implemented. */ - fadt->smi_cmd = 0x00; - } fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 5015659..e5ad336 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -8,11 +8,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + 0x4; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 621bf68..57ff9ab 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -14,11 +14,6 @@ struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 8005fe1..1409d18 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -10,11 +10,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 005fdb6..0e4dd76 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -10,11 +10,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index a917fb8..d750890 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index ee7b309..eaea091 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/74600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Gerrit-Change-Number: 74600 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit April 2023