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Change subject: WIP:soc/amd/morgana: Move PSP FWs to 0x20000
......................................................................
Abandoned
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Hello Tarun Tuli, Vinay Kumar, AlanKY Lee, Vidya Gopalakrishnan,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/skolas: update PL1 minimum value
......................................................................
mb/google/brya/var/skolas: update PL1 minimum value
Update Power Limit1 (PL1) minimum value to 15W based on the skolas design.
BRANCH=None
BUG=b:235311241
TEST=Built and tested on Skolas system
Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/brya/variants/skolas/overridetree.cb
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/72727/2
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Hello build bot (Jenkins), Tarun Tuli, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/skolas: update dptf thermal settings
......................................................................
mb/google/brya/var/skolas: update dptf thermal settings
Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast. This change is based on the discussion on
bug:235311241 comment#7.
BRANCH=None
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Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
---
M src/mainboard/google/brya/variants/skolas/overridetree.cb
1 file changed, 58 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/71692/4
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Change subject: mb/google/nissa/var/craask: Add DPTF settings for 15W CPU
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Patch Set 9: Code-Review+2
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Change subject: mb/google/nissa/var/craask: Add DPTF settings for 15W CPU
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Change subject: mb/google/nissa/var/craask: Add DPTF settings for 15W CPU
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Patch Set 9: Code-Review+1
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Change subject: soc/intel/xeon_sp: add MSR definition for SPR-SP
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/72611/comment/2e85a9e1_85614fde
PS1, Line 44: #if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
> Sounds good to me
Agreed. The problems found by David is due to spr has different arrangement of registers with previous platforms. Using #if to maintain all discrepancies in a single header might not friendly for maintenance and code review.
// In msr.h
#if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
#include <soc/msr_spr.h>
#elif (CONFIG(SOC_INTEL_COOPERLAKE_SP))
#include <soc/msr_cpx.h>
#elif (CONFIG(SOC_INTEL_SKYLAKE_SP))
#include <soc/msr_skx.h>
#endif
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Change subject: amdfwtool: Add entry RIB whose subprog equals 1
......................................................................
Patch Set 3:
(1 comment)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/72507/comment/fb501930_6a0880f0
PS2, Line 414: } else if (strcmp(fw_name, "PSP_RIB_FILE") == 0) {
> for consistency i'd rename this one to PSP_RIB_FILE_SUB0
Does this SUB1 often happen?
For most cased, it might be confused.
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