coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[S] Change in coreboot[master]: soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUS
by Rex-BC Chen (Code Review) 02 Feb '23

02 Feb '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72641 ) Change subject: soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUS ...................................................................... soc/mediatek/mt8188: Remove the GPIO setting of USB1_DRV_VBUS USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS. TEST=read usb data successfully. BUG=b:236331724 Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/usb.c 1 file changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/usb.c b/src/soc/mediatek/mt8188/usb.c index 6c575cf..2312e2d 100644 --- a/src/soc/mediatek/mt8188/usb.c +++ b/src/soc/mediatek/mt8188/usb.c @@ -14,7 +14,4 @@ void mtk_usb_prepare(void) { mt_pll_set_usb_clock(); - - /* usb drvvbus for 5v power */ - gpio_output(GPIO(USB1_DRV_VBUS), 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/72641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff Gerrit-Change-Number: 72641 Gerrit-PatchSet: 3 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/geralt: Add USB3 HUB reset funtion to bootblock
by Rex-BC Chen (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Liju-Clr Chen. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72594 ) Change subject: mb/google/geralt: Add USB3 HUB reset funtion to bootblock ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72594/comment/deabc12c_37883d2e PS8, Line 7: funtion > sorry for the typo. will be careful next time. Done https://review.coreboot.org/c/coreboot/+/72594/comment/bb7d3791_9a8527f0 PS8, Line 12: TEST=boot kernel from USB ok > ok Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Gerrit-Change-Number: 72594 Gerrit-PatchSet: 8 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 02:33:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/geralt: Add USB3 HUB reset funtion to bootblock
by Rex-BC Chen (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Liju-Clr Chen. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72594 ) Change subject: mb/google/geralt: Add USB3 HUB reset funtion to bootblock ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72594/comment/6b6d341e_782a08c2 PS8, Line 7: funtion > function sorry for the typo. will be careful next time. https://review.coreboot.org/c/coreboot/+/72594/comment/f7175bc2_8fbd2898 PS8, Line 12: TEST=boot kernel from USB ok > Please elaborate next time. ok -- To view, visit https://review.coreboot.org/c/coreboot/+/72594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Gerrit-Change-Number: 72594 Gerrit-PatchSet: 8 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 02:33:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: amdfwtool: Remove useless printing out
by Bao Zheng (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72724 to review the following change. Change subject: amdfwtool: Remove useless printing out ...................................................................... amdfwtool: Remove useless printing out Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/data_parse.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/72724/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 7268cf8..15296b2 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -374,7 +374,6 @@ fw_type = AMD_FW_MPIO; subprog = 0; } else if (strcmp(fw_name, "TPMLITE_FILE") == 0) { - printf("TPMLITE\n"); fw_type = AMD_FW_TPMLITE; subprog = 0; } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/72724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4 Gerrit-Change-Number: 72724 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: amdfwtool: Add a function to make the calling stack less deep
by Bao Zheng (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Martin L Roth, Marshall Dawson, Zheng Bao. Hello build bot (Jenkins), Jason Glenesk, Martin L Roth, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51881 to look at the new patch set (#4). Change subject: amdfwtool: Add a function to make the calling stack less deep ...................................................................... amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/data_parse.c 1 file changed, 49 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/51881/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Gerrit-Change-Number: 51881 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Enable V1p05-PHY supply external FET control
by Sukumar Ghorai (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Subrata Banik, Kapil Porwal. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72709 ) Change subject: soc/intel/meteorlake: Enable V1p05-PHY supply external FET control ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/72709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04 Gerrit-Change-Number: 72709 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 02:32:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/xeon_sp/include: Update files under include folder
by Simon Chou (Code Review) 02 Feb '23

02 Feb '23

Simon Chou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/71966 ) Change subject: soc/intel/xeon_sp/include: Update files under include folder ...................................................................... Abandoned obsoleted by [CB:72611], [CB:72612], [CB:72613], [CB:72618] -- To view, visit https://review.coreboot.org/c/coreboot/+/71966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f076ca7de02b1e17ff798dcfb445e595d17306 Gerrit-Change-Number: 71966 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TimLiu-SMCI Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: [WIP] soc/intel/meteorlake: Enable Trace Hub
by Pratikkumar V Prajapati (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72723 ) Change subject: [WIP] soc/intel/meteorlake: Enable Trace Hub ...................................................................... [WIP] soc/intel/meteorlake: Enable Trace Hub Change-Id: I335b15788fefb83f9f62560b160d1e84494b262a Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/72723/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index c00be8f..86646fd 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -94,6 +94,7 @@ select UDELAY_TSC select UDK_202111_BINDING select X86_INIT_NEED_1_SIPI + select SOC_INTEL_COMMON_BLOCK_TRACEHUB config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT bool diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 0962a7c..649a196 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -170,6 +170,6 @@ device pci 1f.4 alias smbus off end device pci 1f.5 alias fast_spi on end device pci 1f.6 alias gbe off end - device pci 1f.7 alias npk off end + device pci 1f.7 alias npk on end end end diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index c01896f..c8f3468 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -275,7 +275,8 @@ const struct soc_intel_meteorlake_config *config) { /* Set debug probe type */ - m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_METEORLAKE_DEBUG_CONSENT; + m_cfg->PlatformDebugOption = 2; + m_cfg->DciEn = 1; /* CrashLog config */ if (CONFIG(SOC_INTEL_CRASHLOG)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/72723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I335b15788fefb83f9f62560b160d1e84494b262a Gerrit-Change-Number: 72723 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: [WIP] soc/intel/common: Add Intel Trace Hub driver
by Pratikkumar V Prajapati (Code Review) 02 Feb '23

02 Feb '23

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72722 ) Change subject: [WIP] soc/intel/common: Add Intel Trace Hub driver ...................................................................... [WIP] soc/intel/common: Add Intel Trace Hub driver From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/include/device/pci_ids.h A src/soc/intel/common/block/tracehub/Kconfig A src/soc/intel/common/block/tracehub/Makefile.inc A src/soc/intel/common/block/tracehub/tracehub.c 4 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/72722/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dbc1706..d620de3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4472,6 +4472,9 @@ #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d +/* Intel Tracehub*/ +#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 + /* Intel Ethernet Controller device Ids */ #define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32 #define PCI_DID_INTEL_EHL_GBE_PSE_0 0x4BA0 diff --git a/src/soc/intel/common/block/tracehub/Kconfig b/src/soc/intel/common/block/tracehub/Kconfig new file mode 100644 index 0000000..3034229 --- /dev/null +++ b/src/soc/intel/common/block/tracehub/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_TRACEHUB + bool + default n + help + Enable Intel Trace Hub (TH). diff --git a/src/soc/intel/common/block/tracehub/Makefile.inc b/src/soc/intel/common/block/tracehub/Makefile.inc new file mode 100644 index 0000000..aabed87 --- /dev/null +++ b/src/soc/intel/common/block/tracehub/Makefile.inc @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TRACEHUB) += tracehub.c diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c new file mode 100644 index 0000000..282c284 --- /dev/null +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> + +static const uint8_t fsp_tracehub_guid[16] = { + 0x09, 0x59, 0xb3, 0x5f, 0x1c, 0x5a, 0x31, 0x4a, + 0xad, 0xaf, 0x57, 0x7b, 0x54, 0x68, 0x26, 0x3f, +}; + +static void tracehub_read_resources(struct device *dev) +{ + const struct hob_resource *tracehub_info_hob; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* + * Find the Trace Hub HOB generated by Intel FSP. If the Trace Hub + * is configured to save data in DRAM, FSP will generate this HOB. + * This HOB contains address and length of the memory region used + * by Trace Hub to save traces. Mark this memory region as reserved. + */ + tracehub_info_hob = fsp_find_resource_hob_by_guid(fsp_tracehub_guid); + if (!tracehub_info_hob) { + printk(BIOS_INFO, "Tracehub HOB not found\n"); + return; + } + + printk(BIOS_DEBUG, "Trace Hub HOB found: addr=0x%08llx length=0x%08llx\n", + tracehub_info_hob->addr, tracehub_info_hob->length); + + reserved_ram_resource_kb(dev, 0, tracehub_info_hob->addr / KiB, + tracehub_info_hob->length / KiB); +} + +static struct device_operations dev_ops = { + .read_resources = tracehub_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_MTL_TRACEHUB, + 0 +}; + +static const struct pci_driver tracehub_driver __pci_driver = { + .ops = &dev_ops, + .vendor = PCI_VID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/72722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Gerrit-Change-Number: 72722 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUID
by Pratikkumar V Prajapati (Code Review) 02 Feb '23

02 Feb '23

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72721 ) Change subject: drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUID ...................................................................... drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUID The API finds the FSP resource HOB for the given GUID. Returns the pointer to the HOB if found, otherwise NULL Change-Id: I4ebc9b7d214e5fc731ae45f28e7f5732a7635cbc Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/72721/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index aae1ff8..227f412 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -245,6 +245,20 @@ return NULL; } +const void *fsp_find_resource_hob_by_guid(const uint8_t *guid) +{ + const struct hob_header *hob_iterator; + const struct hob_resource *res_hob; + + if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) + return NULL; + + if (fsp_hob_iterator_get_next_guid_resource(&hob_iterator, guid, &res_hob) == CB_SUCCESS) + return res_hob; + + return NULL; +} + static void display_fsp_version_info_hob(const void *hob) { #if CONFIG(DISPLAY_FSP_VERSION_INFO) || CONFIG(DISPLAY_FSP_VERSION_INFO_2) diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 566fad9..6c9d397 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -143,6 +143,11 @@ void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); void soc_validate_fspm_header(const struct fsp_header *hdr); +/* + * This function finds the FSP resource HOB for the given GUID. + * Returns the pointer to the HOB if found, otherwise NULL + */ +const void *fsp_find_resource_hob_by_guid(const uint8_t *guid); /* Fill in header and validate a loaded FSP component. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_blob, size_t size); -- To view, visit https://review.coreboot.org/c/coreboot/+/72721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ebc9b7d214e5fc731ae45f28e7f5732a7635cbc Gerrit-Change-Number: 72721 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023