coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3036 discussions

[S] Change in coreboot[main]: vendorcode/amd/opensil: Implement cbmem_top_chipset
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76513?usp=email ) Change subject: vendorcode/amd/opensil: Implement cbmem_top_chipset ...................................................................... vendorcode/amd/opensil: Implement cbmem_top_chipset Use an xPRF call to get the top of lower DRAM. Organize Makefile to keep romstage/ramstage components separate. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/vendorcode/amd/opensil/genoa_poc/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/romstage.c 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc index 5c7117a..c5742b5 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc +++ b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc @@ -3,8 +3,12 @@ CPPFLAGS_ramstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF CPPFLAGS_romstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF -ramstage-y += opensil_console.c romstage-y += opensil_console.c +romstage-y += romstage.c + +ramstage-y += opensil_console.c $(obj)/romstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas +$(obj)/romstage/vendorcode/amd/opensil/genoa_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas + $(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/genoa_poc/romstage.c b/src/vendorcode/amd/opensil/genoa_poc/romstage.c new file mode 100644 index 0000000..e55ed1b --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include "opensil_console.h" +#include <xSIM-api.h> +#include <xPRF-api.h> + +uintptr_t cbmem_top_chipset(void) +{ + SilDebugSetup(HostDebugService); + uintptr_t top_mem = xPrfGetLowUsableDramAddress(0); + printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", top_mem); + + /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so + account for potentially ill aligned TOP_MEM. */ + if (CONFIG_SMM_TSEG_SIZE) { + top_mem -= CONFIG_SMM_TSEG_SIZE; + top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); + } + + return top_mem; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Gerrit-Change-Number: 76513 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79313?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id f2b01bf0: 2023-10-27 Julius Werner firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY to commit id ba7fd22d: 2023-11-27 Julius Werner Makefile: Always link libdl This brings in 54 new commits: ba7fd22d Makefile: Always link libdl 1b30d195 sign_official_build: sign_update_payload with pkcs11 ca7a1427 sign_firmware: support loem key config a9623573 sign_official_build: add keys to default key config d41497dc sign_official_build: support loem key config da2450db sign_official_build: support sign with .vbprik2 files ee326142 getversion: Make reproducible 8aaf9e32 futility: fix a typo in help message of `read` 9ce505f4 futility: Fix incorrect warning about signing length 23a0ce4e scripts: add lib/keycfg.sh 2e34330b Makefile: Fix firmware build for FIRMWARE_ARCH=arm64 fd5937d1 tests/futility/test_show_and_verify: Add test cases for invalid data key 00aa0626 futility/cmd_vbutil_kernel: Drop --pad option for --verify c661ab76 futility/cmd_show: Drop --pad option c70511d7 tests/futility/test_show_and_verify: Add test cases for kernel vblocks c9100f46 signer: Use compression flags stored in the metadata file f1f3076f vboot: Add vb_keyb_from_private_key c39a2fc1 host: support signing with pkcs11 key for vbprik2 c6d44076 vboot: merge reading function of vb2/vb21 private key 6b8e759f vboot: replace custom prefix "pkcs11" to "remote" 481440d0 futility: Prefer to flash over CCD instead of C2D2 1244c06f futility/cmd_dump_fmap: Print an error if FMAP header not found cab69289 futility/cmd_show: Fix parseable output for kernel preamble flags 71a03dc6 futility/cmd_show: Make preamble parseable output consistent bdac62a4 futility/cmd_show: Make 'show' return 0 for invalid kernel body 135df2d7 futility/cmd_show: Show parseable "keyblock::valid" for valid keyblock 37f37fcd futility/cmd_show: Fix output for firmware body signature 79c244ff tests/futility/test_show_and_verify: Add test cases for bios_brya_mp.bin d4b6560f signer: Update mkfs.erofs pcluster value to 32K f79a2432 futility/cmd_sign: Fix a space in usage text a307fcb5 futility: updater: rename --ccd to --ccd_without_servod 6b9f66d3 futility: updater: Fix malloc overflow due to broken keyblock a94a784c updater: update: Support multiple Servos without --servo_port 25875bef tests/futility: Add test cases for VBOOT_CBFS_INTEGRATION 5f8e3973 futility/cmd_show: Fix typo "metatadata" 9d30a01f futility: Trim trailing spaces in kernel config c59794a6 sign_uefi: Support signing via pkcs11 68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI 6b9d624b sign_uefi: Pass each key path separately 483f65e4 sign_official_build.sh: properly show errors on loem issues 516ee7bc sign_uefi: Use named args instead of positional 0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder 46f5aab8 image_signing: support multiple release names f13af139 sign_official_build: Sudo invocation within bits of android signing 3f165374 futility: updater: Add optional serial number argument to --ccd 64379cc6 sign_official_build: add --debug flag 7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc 0e27cdff vboot_reference-sys: Add vboot_host.h 2c82e73c Override use_apksigner FLAGS b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK 0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin 68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh 8daf1474 tests/futility: Move 'futility show' tests to a separate file 34190e3d futility: Exit with error when metadata hash verification not supported 967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size() Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79313 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Uwe Poeche: Looks good to me, but someone else must approve diff --git a/3rdparty/vboot b/3rdparty/vboot index c59794a..ba7fd22 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit c59794a6e939af42f36086d5fd656ee7496eb4b6 +Subproject commit ba7fd22d3dd659b3ab42ad66f22169a6ce0f4dfe -- To view, visit https://review.coreboot.org/c/coreboot/+/79313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385 Gerrit-Change-Number: 79313 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: Update arm-trusted-firmware submodule to upstream master
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79333?usp=email ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 88b2d8134: 2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration) to commit id e7486343d: 2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration) This brings in 451 new commits. Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79333 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 88b2d81..e748634 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 88b2d81345dfd84902aae586a743d00ac5df2f48 +Subproject commit e7486343d46a0d60047233adfd8a64436bbac1fd -- To view, visit https://review.coreboot.org/c/coreboot/+/79333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f Gerrit-Change-Number: 79333 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/corsola: Use fw_config to differentiate audio amps
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79309?usp=email ) Change subject: mb/google/corsola: Use fw_config to differentiate audio amps ...................................................................... mb/google/corsola: Use fw_config to differentiate audio amps Use fw_config to differentiate audio amps instead of the kconfig option. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309 Reviewed-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c 2 files changed, 11 insertions(+), 3 deletions(-) Approvals: Ruihai Zhou: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 0e8bb91..300ba7b 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,4 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +fw_config + field AUDIO_AMP 28 29 + option AMP_ALC1019 0 + option AMP_ALC5645 1 + end +end chip soc/mediatek/mt8186 device cpu_cluster 0 on end diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a6659a5..37f3a70 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> +#include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> #include <soc/i2c.h> @@ -51,10 +52,11 @@ setup_usb_host(); - if (CONFIG(BOARD_GOOGLE_CHINCHOU)) - configure_alc5645(); - else + if (!fw_config_is_provisioned() || + fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019))) configure_alc1019(); + else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) + configure_alc5645(); if (spm_init()) printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/79309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Gerrit-Change-Number: 79309 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Add LTE only daughterboard support
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79297?usp=email ) Change subject: mb/google/nissa/var/quandiso: Add LTE only daughterboard support ...................................................................... mb/google/nissa/var/quandiso: Add LTE only daughterboard support Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Shawn Ku <shawnku(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/quandiso/fw_config.c M src/mainboard/google/brya/variants/quandiso/overridetree.cb 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Shawn Ku: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/quandiso/fw_config.c b/src/mainboard/google/brya/variants/quandiso/fw_config.c index c5ac0d2..dc286a8 100644 --- a/src/mainboard/google/brya/variants/quandiso/fw_config.c +++ b/src/mainboard/google/brya/variants/quandiso/fw_config.c @@ -75,7 +75,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && + !fw_config_probe(FW_CONFIG(DB_USB, DB_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 29a4cee..205fd2b 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -2,7 +2,7 @@ field DB_USB 0 1 option DB_NONE 0 option DB_1C_1A 1 - option DB_1C 2 + option DB_LTE 2 option DB_1C_LTE 3 end field WIFI_SAR_ID 2 3 @@ -333,6 +333,7 @@ register "reg_adv_ctrl19" = "0xf0" register "reg_adv_ctrl20" = "0xf0" device i2c 28 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end @@ -444,7 +445,6 @@ use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -468,7 +468,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -492,7 +491,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -565,6 +563,7 @@ register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port2 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Gerrit-Change-Number: 79297 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/galdos/var/lars: Implement touchscreen power sequencing
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79311?usp=email ) Change subject: mb/google/galdos/var/lars: Implement touchscreen power sequencing ...................................................................... mb/google/galdos/var/lars: Implement touchscreen power sequencing Since lars has two touchscreen options, we need to determine which (if any) are present on a given device at runtime so that there are not multiple ACPI touchscreen devices (as it makes Windows unhappy). Implement power sequencing and runtime detection for both touchscreen options. TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected and functional under both OSes. Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/overridetree.cb 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index 5ff059b..611ee24 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -216,6 +216,10 @@ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), + +/* touchscreen enable, hold in reset */ +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), +/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 0, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb index 717ea53..2616044 100644 --- a/src/mainboard/google/glados/variants/lars/overridetree.cb +++ b/src/mainboard/google/glados/variants/lars/overridetree.cb @@ -18,12 +18,24 @@ register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "detect" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E23)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" device i2c 10 on end end chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "detect" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E23)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" device i2c 34 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd Gerrit-Change-Number: 79311 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: mb/google/glados/var/lars: Add Melfas touchscreen
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79310?usp=email ) Change subject: mb/google/glados/var/lars: Add Melfas touchscreen ...................................................................... mb/google/glados/var/lars: Add Melfas touchscreen LARS has a Melfas touchscreen option, so add an entry for it. Adapted from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f ("Chell: Update DPTF parameters for CPU"). TEST=build/boot Linux on google/lars with Melfas touchscreen, verify functional. Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/glados/variants/lars/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb index 122cfe6..717ea53 100644 --- a/src/mainboard/google/glados/variants/lars/overridetree.cb +++ b/src/mainboard/google/glados/variants/lars/overridetree.cb @@ -20,6 +20,12 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 34 on end + end end device ref i2c1 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/79310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751 Gerrit-Change-Number: 79310 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79334?usp=email ) Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1 ...................................................................... mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1 The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus interface is per default write-protected in FSP. This avoids that an SPD-EEPROM on a DRAM module gets overwritten by the host. On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM available. Nevertheless, there is a general purpose EEPROM on the same address available which needs to stay writeable. This patch disables the default-enabled write protect feature for the SPD-EEPROM addresses just for mc_ehl1. Test=Boot into Linux and make sure a write access into the EEPROM is possible. Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jan Samek: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 28fca2d..d386d75 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -38,4 +38,8 @@ /* Enable Row-Hammer prevention */ memupd->FspmConfig.RhPrevention = 1; + if (CONFIG(BOARD_SIEMENS_MC_EHL1)) { + /* Allow writes to EEPROM addresses 0x50..0x57. */ + memupd->FspmConfig.SmbusSpdWriteDisable = 0; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/79334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Gerrit-Change-Number: 79334 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79163?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device ...................................................................... mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device Enable MIPI camera for anraggar project. Sensor: OV13B10-GA5A Driver: DW9714V EEPROM: GT24P64E Ref to SCH, use MIPI 4-lane serial output interface. BUG=b:309518095 TEST=Google Camera app working Checking log with: coreboot log: \_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h kernel log: kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1 cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom cros_camera_service[4755]: Probing media device '/dev/media0' cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17) cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17 Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arec Kao <arec.kao(a)intel.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 27 insertions(+), 21 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Arec Kao: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index cdbb72f..b01bc2c 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -32,7 +32,7 @@ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ - PAD_CFG_GPO_LOCK(GPP_D13, 0, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG), /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */ PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), @@ -48,7 +48,7 @@ PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD ==> EN_PP2800_AVDD*/ + /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */ PAD_CFG_GPO(GPP_F18, 0, DEEP), /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index defb8e6..30c3c1b 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -207,7 +207,7 @@ register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" register "cio2_prt[0]" = "1" device generic 0 on end @@ -244,18 +244,17 @@ end device ref i2c2 on chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" + register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" + register "chip_name" = ""Ov 13b10 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" + register "ssdb.lanes_used" = "4" register "ssdb.vcm_type" = "0x0C" register "vcm_name" = ""VCM0"" register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "link_freq[0]" = "560 * MHz" register "remote_name" = ""IPU0"" register "has_power_resource" = "1" @@ -263,17 +262,16 @@ register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "4" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF register "off_seq.ops_cnt" = "4" @@ -285,30 +283,38 @@ device i2c 36 on end end chip drivers/intel/mipi_camera - register "acpi_uid" = "3" + register "acpi_uid" = "2" register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW AF DAC"" + register "chip_name" = ""DW9714 VCM "" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_AFVDD + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" - register "chip_name" = ""GT24C08"" + register "chip_name" = ""GT24P64E"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c08"" + register "nvm_compat" = ""atmel,24c64"" device i2c 50 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Gerrit-Change-Number: 79163 Gerrit-PatchSet: 5 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Arec Kao <arec.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable CNVi Bluetooth
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79055?usp=email ) Change subject: mb/google/nissa/var/anraggar: Enable CNVi Bluetooth ...................................................................... mb/google/nissa/var/anraggar: Enable CNVi Bluetooth Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC, and the relevant configuration needs to be modified in overridtre.cb. BUG=b:304920262 TEST=lsusb ID 8087:0033 Intel Corp. rfkill list hci0:Bluetooth Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 13 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 6eac21a..cdbb72f 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A7 : NC ==> LTE_Present */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), /* A18 : NC ==> HDMI_HPD_SRC*/ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), @@ -80,8 +82,8 @@ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* F16 : NC ==> WWAN_PWR_ENABLE */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* D6 : NC ==> WWAN_PWR_ENABLE */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 16da214..defb8e6 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -409,7 +409,8 @@ [3] = USB2_PORT_MID(OC_SKIP), /* Type-A DB (6.2 inch) */ [4] = USB2_PORT_SHORT(OC_SKIP), /* LTE (3.3 inch) */ [5] = USB2_PORT_SHORT(OC_SKIP), /* UFC (3.7 inch) */ - [7] = USB2_PORT_SHORT(OC_SKIP), /* BT (2.5 inch) */ + [7] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for PCIe WLAN (2.5 inch) */ + [9] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for CNVi WLAN */ }" chip drivers/usb/acpi device ref xhci_root_hub on @@ -452,12 +453,18 @@ device ref usb2_port6 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" + register "desc" = ""PCIe Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port8 on end end chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/79055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Gerrit-Change-Number: 79055 Gerrit-PatchSet: 7 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
304
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023