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Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+2 by Julius Werner, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins)
Change subject: libpayload: Fix the stack and data labels
......................................................................
libpayload: Fix the stack and data labels
We should make sure _stack/_estack and the other labels are consistent.
And _data & _edata is also useful to clean up the sensitive data on the
data section.
BUG=b:248610274
TEST=emerge-cherry libpayload
BRANCH=none
Cq-Depend: chromium:5052462
Change-Id: I589040f4db60b35813ea9f4ba9503244bd7def00
Signed-off-by: Yi Chou <yich(a)google.com>
---
M payloads/libpayload/arch/arm/head.S
M payloads/libpayload/arch/arm/libpayload.ldscript
M payloads/libpayload/arch/arm64/head.S
M payloads/libpayload/arch/arm64/libpayload.ldscript
M payloads/libpayload/arch/x86/head.S
M payloads/libpayload/arch/x86/libpayload.ldscript
6 files changed, 33 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/79144/8
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79348?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79348/comment/2e35e97c_7aabe037 :
PS1, Line 9: Update BND_NORTH_APB2_S's domain 5 permission to allow the access from
: APU.
Why? Otherwise no graphics is shown? Please elaborate on the problem.
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Change subject: mb/google/brox: Update storage settings for SSD and UFS
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79295/comment/36abb0d8_4b60eeb5 :
PS3, Line 16: unexpect
> Done.
A revision/version would be nice to have.
File src/mainboard/google/brox/Kconfig:
https://review.coreboot.org/c/coreboot/+/79295/comment/a5f55737_c9048302 :
PS3, Line 50: select DRIVERS_INTEL_ISH
> This is required for enabling UFS.
Yes, so it could be ordered before.
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Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79330?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/rex/var/screebo: Override power limits
......................................................................
mb/google/rex/var/screebo: Override power limits
This patch modifies the power limits value to enhance power management
for the google/screebo variant.
Additionally, rearrange the include header files alphabetically.
BUG=b:313667378
TEST=Able to boot google/screebo with modified power limits.
Before:
[DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/
ramstage.c/variant_devtree_update called
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
After:
[INFO ] Overriding power limits PL1 (mW) (10000, 15000)
PL2 (mW) (40000, 40000) PL4 (W) (84)
Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/screebo/variant.c
1 file changed, 65 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79330/3
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79335?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
......................................................................
mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance.
The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W).
BUG=b:312321601
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Built and booted into OS, and confirm MSR PL1=17W correctly.
Change-Id: If7874d26038118c5605cf0721c30e681b45123fe
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/marasov/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Daniel Peng: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index a8c1c06..6c1f3f9 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -134,6 +134,12 @@
register "tcc_offset" = "5" # TCC of 100
+ register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+ .tdp_pl1_override = 17,
+ .tdp_pl2_override = 55,
+ .tdp_pl4 = 114,
+ }"
+
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
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