coreboot-gerrit November 2023

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Bao Zheng (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Bao Zheng, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Simon Glass, Tim Wawrzynczak, Zheng Bao. Hello Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Simon Glass, Tim Wawrzynczak, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79174?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... soc/amd: Add DBG2 ACPI table Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/common/block/acpi/tables.c 3 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/79174/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya/var/dochi: Update overridetree for type c1
by Morris Hsu (Code Review) 30 Nov '23

30 Nov '23

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79343?usp=email ) Change subject: mb/google/brya/var/dochi: Update overridetree for type c1 ...................................................................... mb/google/brya/var/dochi: Update overridetree for type c1 Update overridetree to correct type c1 does not show HDMI. BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dochi/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/79343/1 diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb index cc74f8d..19ace7b 100644 --- a/src/mainboard/google/brya/variants/dochi/overridetree.cb +++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb @@ -18,14 +18,14 @@ # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. - # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2. - # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0" - # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # Bits (0,1) allocated for TCSS Port1 configuration, Bits (4,5)for TCSS Port3. + # TcssAuxOri = 010001b + # Bit0,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0" + # Bit1,Bit5 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector - register "tcss_aux_ori" = "0x5" + register "tcss_aux_ori" = "0x11" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Gerrit-Change-Number: 79343 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION config
by Subrata Banik (Code Review) 30 Nov '23

30 Nov '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79338?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION config ...................................................................... mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION config This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards to retrieve the ISH version and store it into memory. Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms with ISH support (DRIVERS_INTEL_ISH). Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config selection for the Nissa baseboard is no longer needed. BUG=b:280722061 TEST=Able to build and boot google/marasov. Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 757cfc4..c6a4987 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 if SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_STORE_ISH_FW_VERSION if DRIVERS_INTEL_ISH config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n @@ -92,7 +93,6 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - select SOC_INTEL_STORE_ISH_FW_VERSION select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE -- To view, visit https://review.coreboot.org/c/coreboot/+/79338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595 Gerrit-Change-Number: 79338 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits
by Subrata Banik (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79330?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/var/screebo: Override power limits ...................................................................... mb/google/rex/var/screebo: Override power limits This patch modifies the power limits value to enhance power management for the google/screebo variant. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/screebo/variant.c 1 file changed, 65 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79330/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Gerrit-Change-Number: 79330 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/docker/fedora: Add initial Dockerfile
by Felix Singer (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79316?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/docker/fedora: Add initial Dockerfile ...................................................................... util/docker/fedora: Add initial Dockerfile Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- A util/docker/fedora/Dockerfile 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/79316/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Gerrit-Change-Number: 79316 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: 3rdparty/intel-sec-tools: Update to v2.7.0 tag
by Felix Singer (Code Review) 30 Nov '23

30 Nov '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79318?usp=email ) Change subject: 3rdparty/intel-sec-tools: Update to v2.7.0 tag ...................................................................... 3rdparty/intel-sec-tools: Update to v2.7.0 tag Change-Id: I4de90f6c1363546a5043dae5cceb37356a099328 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/intel-sec-tools 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/79318/1 diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools index 0031ac7..237c035 160000 --- a/3rdparty/intel-sec-tools +++ b/3rdparty/intel-sec-tools @@ -1 +1 @@ -Subproject commit 0031ac73447baeb197fb2d80e5fba2470716e76d +Subproject commit 237c035e4f122f70f850dacdc9750ce42bce0d81 -- To view, visit https://review.coreboot.org/c/coreboot/+/79318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4de90f6c1363546a5043dae5cceb37356a099328 Gerrit-Change-Number: 79318 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
by Felix Singer (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Arthur Heymans, Maximilian Brune, Paul Menzel. Hello Arthur Heymans, Maximilian Brune, Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78884?usp=email to look at the new patch set (#4). Change subject: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6 ...................................................................... util/crossgcc: Update LLVM from 16.0.6 to 17.0.6 Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum 11 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/78884/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Gerrit-Change-Number: 78884 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/google/brox: Update storage settings for SSD and UFS
by Ivy Jian (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Paul Menzel. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79295?usp=email ) Change subject: mb/google/brox: Update storage settings for SSD and UFS ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79295/comment/b8bf230f_35e98e24 : PS3, Line 10: configured > configure Done. https://review.coreboot.org/c/coreboot/+/79295/comment/bd3a6867_bf85039d : PS3, Line 11: settings. > … according to schematic <file name>. Done. https://review.coreboot.org/c/coreboot/+/79295/comment/6fcedb0a_fc82e339 : PS3, Line 16: unexpect > unexpected Done. https://review.coreboot.org/c/coreboot/+/79295/comment/75907a2f_93b51b5b : PS3, Line 20: TEST=emerge-brox coreboot > Don’t you have access yet? emerge-brox coreboot to make sure no build error. File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/79295/comment/5ee02632_c0e179b7 : PS3, Line 50: select DRIVERS_INTEL_ISH > Maybe make that a separate commit. This is required for enabling UFS. -- To view, visit https://review.coreboot.org/c/coreboot/+/79295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Gerrit-Change-Number: 79295 Gerrit-PatchSet: 4 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yen-hsing Lee <yen-hsing.lee(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 30 Nov 2023 01:12:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brox: Update storage settings for SSD and UFS
by Karthik Ramasubramanian (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Ivy Jian. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79295?usp=email ) Change subject: mb/google/brox: Update storage settings for SSD and UFS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Gerrit-Change-Number: 79295 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yen-hsing Lee <yen-hsing.lee(a)quanta.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 00:28:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/docker/fedora: Add initial Dockerfile
by Felix Singer (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79316?usp=email ) Change subject: util/docker/fedora: Add initial Dockerfile ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Build-tests missing -- To view, visit https://review.coreboot.org/c/coreboot/+/79316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Gerrit-Change-Number: 79316 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Nov 2023 23:39:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2023