coreboot-gerrit November 2023

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Tune eMMC DLL values
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78851?usp=email ) Change subject: mb/google/nissa/var/anraggar: Tune eMMC DLL values ...................................................................... mb/google/nissa/var/anraggar: Tune eMMC DLL values Anraggar cannot boot into OS and kernel loading failure. Update eMMC DLL values to improve initialization reliability - Sending different speed TX/RX command/data signal to eMMC and check the response is success or not. - Collecting every eMMC that use for the project - Based on above result to provide a fine tune DLL values BUG=b:308366637 TEST=Cold reboot stress test over 2500 cycles Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index e77b676..16da214 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -1,6 +1,51 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10051" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. -- To view, visit https://review.coreboot.org/c/coreboot/+/78851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Gerrit-Change-Number: 78851 Gerrit-PatchSet: 9 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vendorcode/amd/opensil/genoa: Implement console callback
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76512?usp=email ) Change subject: vendorcode/amd/opensil/genoa: Implement console callback ...................................................................... vendorcode/amd/opensil/genoa: Implement console callback OpenSIL has an API to call back into the host firmware to print to the console. These could be moved to a common directory when there are more openSIL implementations to see if it is actually common. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/vendorcode/amd/opensil/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/filter.h M src/vendorcode/amd/opensil/genoa_poc/meson_cross.template A src/vendorcode/amd/opensil/genoa_poc/opensil_console.c A src/vendorcode/amd/opensil/genoa_poc/opensil_console.h 6 files changed, 89 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/Makefile.inc b/src/vendorcode/amd/opensil/Makefile.inc index 5afe075..ca206aa 100644 --- a/src/vendorcode/amd/opensil/Makefile.inc +++ b/src/vendorcode/amd/opensil/Makefile.inc @@ -8,6 +8,8 @@ opensil_dir := $(call strip_quotes,$(CONFIG_AMD_OPENSIL_PATH)) +subdirs-$(CONFIG_SOC_AMD_OPENSIL_GENOA) += genoa_poc + ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cpu_family_string="x86" cpu_string="i686" diff --git a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc new file mode 100644 index 0000000..5c7117a --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_ramstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF +CPPFLAGS_romstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF + +ramstage-y += opensil_console.c +romstage-y += opensil_console.c + +$(obj)/romstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas +$(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/genoa_poc/filter.h b/src/vendorcode/amd/opensil/genoa_poc/filter.h new file mode 100644 index 0000000..b4a94a6 --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/filter.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Keep this in sync with opensil SilCommon.h file */ +#define DEBUG_FILTER_APOB 0x00000001UL +#define DEBUG_FILTER_NBIO 0x00000002UL +#define DEBUG_FILTER_CCX 0x00000004UL +#define DEBUG_FILTER_SMU 0x00000008UL +#define DEBUG_FILTER_DF 0x00000010UL +#define DEBUG_FILTER_MEM 0x00000040UL +#define DEBUG_FILTER_FCH 0x00000080UL +#define DEBUG_FILTER_RAS 0x00000100UL + +#define SIL_DEBUG(topic) (CONFIG(OPENSIL_DEBUG_##topic) ? DEBUG_FILTER_##topic : 0) + +#define SIL_DEBUG_MODULE_FILTER ( \ + SIL_DEBUG(APOB) | \ + SIL_DEBUG(NBIO) | \ + SIL_DEBUG(CCX) | \ + SIL_DEBUG(SMU) | \ + SIL_DEBUG(DF) | \ + SIL_DEBUG(MEM) | \ + SIL_DEBUG(FCH) | \ + SIL_DEBUG(RAS) ) diff --git a/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template b/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template index b457c80..6473b65 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template +++ b/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template @@ -13,6 +13,7 @@ '-include', '##COREBOOT_DIR##/src/include/kconfig.h', '-include', '##OBJPATH##/config.h', '-include', '##COREBOOT_DIR##/src/commonlib/bsd/include/commonlib/bsd/compiler.h', + '-include', '##OPENSIL_DIR##/../filter.h', '-DHAS_STRING_H=1', # openSIL isn't compatible with coreboot's assert implementation, so use special case '-D_PORTING_H_=1', diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil_console.c b/src/vendorcode/amd/opensil/genoa_poc/opensil_console.c new file mode 100644 index 0000000..55a3521 --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil_console.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <console/console.h> +#include "opensil_console.h" +#include <SilCommon.h> + +static int translate_opensil_debug_level(size_t MsgLevel) +{ + switch (MsgLevel) { + case SIL_TRACE_ERROR: + return BIOS_ERR; + case SIL_TRACE_WARNING: + return BIOS_WARNING; + case SIL_TRACE_ENTRY: + case SIL_TRACE_EXIT: + return BIOS_SPEW; + case SIL_TRACE_INFO: + return BIOS_DEBUG; + default: + return BIOS_NEVER; + } +} + +void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message, + const char *Function, size_t Line, ...) +{ + if (!CONFIG(OPENSIL_DEBUG_OUTPUT)) + return; + + const int loglevel = translate_opensil_debug_level(MsgLevel); + + /* print fomatted prefix */ + if (CONFIG(OPENSIL_DEBUG_PREFIX)) + printk(loglevel, "%s%s:%zu:", SilPrefix, Function, Line); + + /* print formatted message */ + va_list args; + va_start(args, Line); + printk(loglevel, Message, args); + va_end(args); +} diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil_console.h b/src/vendorcode/amd/opensil/genoa_poc/opensil_console.h new file mode 100644 index 0000000..d3ffb68 --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil_console.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VENDORCODE_AND_OPENSIL_CONSOLE +#define _VENDORCODE_AND_OPENSIL_CONSOLE + +void HostDebugService(size_t MsgLevel, const char *SilPrefix, const char *Message, + const char *Function, size_t Line, ...); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d Gerrit-Change-Number: 76512 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
by Weimin Wu (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dolan Liu, Eric Lai, Jianeng Ceng, Nick Vaccaro, Paul Menzel, Reka Norman, Shou-Chieh Hsu, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79164?usp=email ) Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > Sorry TPEN is for touch report. Add GPP_C6 for touch report enable, also named stop_gpio. -- To view, visit https://review.coreboot.org/c/coreboot/+/79164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Gerrit-Change-Number: 79164 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 14:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
by Weimin Wu (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dolan Liu, Jianeng Ceng, Nick Vaccaro, Paul Menzel, Reka Norman, Shou-Chieh Hsu, Subrata Banik, Weimin Wu. Hello Dolan Liu, Eric Lai, Jianeng Ceng, Nick Vaccaro, Reka Norman, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79164?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Jianeng Ceng, Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen ...................................................................... mb/google/nissa/var/anraggar: Enable ILITEK touchscreen For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79164/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Gerrit-Change-Number: 79164 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
by Paul Menzel (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Kun Liu, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79320/comment/4b53d872_1111cbe0 : PS1, Line 12: when S0ix returns S0, PERST needs to delay until : Main 3V3 is stable and then pull up This should go into the main body of the commit message. https://review.coreboot.org/c/coreboot/+/79320/comment/7baa78f6_fc15076c : PS1, Line 12: PERST needs to delay until : Main 3V3 is stable Why? According to the schematics? Why 1 ms and not 3 or 5? -- To view, visit https://review.coreboot.org/c/coreboot/+/79320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Gerrit-Change-Number: 79320 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 14:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Update LidStatus UPD dynamically
by Subrata Banik (Code Review) 30 Nov '23

30 Nov '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79352?usp=email ) Change subject: soc/intel/alderlake: Update LidStatus UPD dynamically ...................................................................... soc/intel/alderlake: Update LidStatus UPD dynamically This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/79352/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index d86d62c..4ceda50 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <bootmode.h> #include <bootsplash.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -637,7 +638,7 @@ /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); + s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); s_cfg->PavpEnable = CONFIG(PAVP); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79352?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Gerrit-Change-Number: 79352 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
by Subrata Banik (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Kun Liu, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email ) Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Gerrit-Change-Number: 79320 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 13:25:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
by Rui Zhou (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Kun Liu, Subrata Banik, Tarun. Rui Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email ) Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Gerrit-Change-Number: 79320 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 10:09:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
by Kun Liu (Code Review) 30 Nov '23

30 Nov '23

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email ) Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 ...................................................................... mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 Add delay 1ms after Main 3V3 BUG=b:313976507 TEST=when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79320/1 diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 8be0e85..9aa038e 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -289,6 +289,7 @@ chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "enable_delay_ms" = "1" register "srcclk_pin" = "6" device generic 0 on probe DB_SD SD_GL9750 -- To view, visit https://review.coreboot.org/c/coreboot/+/79320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Gerrit-Change-Number: 79320 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: libpayload: Fix the stack and data labels
by Yi Chou (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Julius Werner, Paul Menzel, Yu-Ping Wu. Yi Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79144?usp=email ) Change subject: libpayload: Fix the stack and data labels ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79144/comment/34fcdb20_25842c89 : PS7, Line 9: the consistency between _stack/_estack and the other : labels > Reads not so fluent to me. Maybe: […] Done File payloads/libpayload/arch/arm/libpayload.ldscript: https://review.coreboot.org/c/coreboot/+/79144/comment/ce6b3761_dd06b29d : PS7, Line 43: . = ALIGN(16); > Excuse my ignorance, but why the alignment? Removed the unnecessary alignment. -- To view, visit https://review.coreboot.org/c/coreboot/+/79144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I589040f4db60b35813ea9f4ba9503244bd7def00 Gerrit-Change-Number: 79144 Gerrit-PatchSet: 8 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 09:53:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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