Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79310?usp=email )
Change subject: mb/google/glados/var/lars: Add Melfas touchscreen
......................................................................
mb/google/glados/var/lars: Add Melfas touchscreen
LARS has a Melfas touchscreen option, so add an entry for it. Adapted
from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f
("Chell: Update DPTF parameters for CPU").
TEST=build/boot Linux on google/lars with Melfas touchscreen, verify
functional.
Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/glados/variants/lars/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb
index 122cfe6..717ea53 100644
--- a/src/mainboard/google/glados/variants/lars/overridetree.cb
+++ b/src/mainboard/google/glados/variants/lars/overridetree.cb
@@ -20,6 +20,12 @@
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
device i2c 10 on end
end
+ chip drivers/i2c/generic
+ register "hid" = ""MLFS0000""
+ register "desc" = ""Melfas Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ device i2c 34 on end
+ end
end
device ref i2c1 on
chip drivers/i2c/generic
--
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Gerrit-Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751
Gerrit-Change-Number: 79310
Gerrit-PatchSet: 2
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79334?usp=email )
Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
......................................................................
mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.
On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.
This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.
Test=Boot into Linux and make sure a write access into the EEPROM is
possible.
Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jan Samek <jan.samek(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jan Samek: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index 28fca2d..d386d75 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -38,4 +38,8 @@
/* Enable Row-Hammer prevention */
memupd->FspmConfig.RhPrevention = 1;
+ if (CONFIG(BOARD_SIEMENS_MC_EHL1)) {
+ /* Allow writes to EEPROM addresses 0x50..0x57. */
+ memupd->FspmConfig.SmbusSpdWriteDisable = 0;
+ }
}
--
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Gerrit-Change-Number: 79334
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Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78851?usp=email )
Change subject: mb/google/nissa/var/anraggar: Tune eMMC DLL values
......................................................................
mb/google/nissa/var/anraggar: Tune eMMC DLL values
Anraggar cannot boot into OS and kernel loading failure.
Update eMMC DLL values to improve initialization reliability
- Sending different speed TX/RX command/data signal to eMMC and check
the response is success or not.
- Collecting every eMMC that use for the project
- Based on above result to provide a fine tune DLL values
BUG=b:308366637
TEST=Cold reboot stress test over 2500 cycles
Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2
Signed-off-by: Simon Yang <simon1.yang(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
1 file changed, 45 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index e77b676..16da214 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -1,6 +1,51 @@
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-42.3.7.
+ # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-42.3.8.
+ # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-42.3.9.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+ # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-42.3.10.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+ # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-42.3.12.
+ # [17:16] stands for Rx Clock before Output Buffer,
+ # 00: Rx clock after output buffer,
+ # 01: Rx clock before output buffer,
+ # 10: Automatic selection based on working mode.
+ # 11: Reserved
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10051"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-42.3.11.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
--
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Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Sorry TPEN is for touch report.
Add GPP_C6 for touch report enable, also named stop_gpio.
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Hello Dolan Liu, Eric Lai, Jianeng Ceng, Nick Vaccaro, Reka Norman, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79164?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Jianeng Ceng, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
......................................................................
mb/google/nissa/var/anraggar: Enable ILITEK touchscreen
For proto PCB:
GPP_C0 for enable power supply which also for sensor subsystem.
GPP_C0 must allways turn power on, so GPP_C6 is not only used
for enable function but also for stop report.
BUG=b:304920262
TEST=1. touchscreen function workable
2. INT pin no active during suspend
Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
2 files changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79164/6
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79320?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79320/comment/4b53d872_1111cbe0 :
PS1, Line 12: when S0ix returns S0, PERST needs to delay until
: Main 3V3 is stable and then pull up
This should go into the main body of the commit message.
https://review.coreboot.org/c/coreboot/+/79320/comment/7baa78f6_fc15076c :
PS1, Line 12: PERST needs to delay until
: Main 3V3 is stable
Why? According to the schematics? Why 1 ms and not 3 or 5?
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