coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 30 Nov '23

30 Nov '23

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP gpios in for romstage. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c 2 files changed, 56 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79355/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 30 Nov '23

30 Nov '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c 2 files changed, 56 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79355/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index daf1b96..92fdecc 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -381,21 +381,33 @@ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* Initialize MEM_STRAPs for memory training in romstage */ + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), +}; + const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } +const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_WEAK_CROS_GPIOS(cros_gpios); - -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c index bcad9b4..25f3092 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c @@ -5,65 +5,64 @@ #include <gpio.h> static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP4X, + .type = MEM_TYPE_LP5X, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = {40, 30, 30, 30, 30}, - }, + /* Leave Rcomp unspecified to use the FSP optimized defaults */ /* DQ byte map */ .lpx_dq_map = { .ddr0 = { - .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, - .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, }, + .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, }, }, .ddr1 = { - .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr2 = { - .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, - .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, }, + .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, }, }, .ddr3 = { - .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, - .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, }, + .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, }, }, .ddr4 = { - .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, - .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, }, + .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, }, }, .ddr5 = { - .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, - .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr6 = { - .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, - .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, }, + .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, }, }, .ddr7 = { - .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, - .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, }, + .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, }, }, }, /* DQS CPU<>DRAM map */ .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = 1, /* Enable Early Command Training */ + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + }; const struct mb_cfg *__weak variant_memory_params(void) @@ -75,16 +74,16 @@ { /* * Memory configuration board straps - * GPIO_MEM_CONFIG_0 GPP_E11 - * GPIO_MEM_CONFIG_1 GPP_E2 - * GPIO_MEM_CONFIG_2 GPP_E1 - * GPIO_MEM_CONFIG_3 GPP_E12 + * GPIO_MEM_CONFIG_0 GPP_E15 + * GPIO_MEM_CONFIG_1 GPP_E12 + * GPIO_MEM_CONFIG_2 GPP_E13 + * GPIO_MEM_CONFIG_3 GPP_E10 */ gpio_t spd_gpios[] = { - GPP_E11, - GPP_E2, - GPP_E1, + GPP_E15, GPP_E12, + GPP_E13, + GPP_E10, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); @@ -92,8 +91,8 @@ bool __weak variant_is_half_populated(void) { - /* GPIO_MEM_CH_SEL GPP_E13 */ - return gpio_get(GPP_E13); + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); } void __weak variant_get_spd_info(struct mem_spd *spd_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Simon Glass (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Bao Zheng, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, Zheng Bao. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... Patch Set 11: Code-Review+1 (1 comment) Patchset: PS11: LGTM. I was hoping to test this today but did not get time. You can try it on skyrim using altfw. Make sure you sync to the latest source. Use the *non-serial* image. Then if U-Boot shows a serial console on boot, all is well. Thank you for doing this! -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 30 Nov 2023 21:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: payloads: Add uefistub payload
by Simon Glass (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Benjamin Doron, Martin L Roth, Maximilian Brune, Patrick Rudolph. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78913?usp=email ) Change subject: payloads: Add uefistub payload ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > I struggle to understand the goal here. […] BTW if the concern is the size, U-Boot can now be built without the cmdline and at some point it will be possible to boot EFI apps in that mode. It makes U-Boot very small -- To view, visit https://review.coreboot.org/c/coreboot/+/78913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1 Gerrit-Change-Number: 78913 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 21:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: payloads: Add uefistub payload
by Simon Glass (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Benjamin Doron, Martin L Roth, Maximilian Brune, Patrick Rudolph. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78913?usp=email ) Change subject: payloads: Add uefistub payload ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I struggle to understand the goal here. We already have U-Boot as a payload which can boot into Linuxboot and provide an EFI interface. Why do we need to pull pieces out of U-Boot to achieve this? It doesn't seem a very friendly approach to me...particularly as the files do not seem to reference U-Bot as the source. But even if they do, this seems like a fork to me. A huge amount of work went into making U-Boot support this feature. Much ongoing work is happening to improve it - the code base is under active development. I believe it would make more sense for coreboot to embrace U-Boot as a first-class coreboot payload, rather than always trying to use something else. I have been trying hard to get U-Boot to work better as a coreboot payload. U-Boot's CI now boots coreboot to check it works on every PR. I would really like to see some reciprocal efforts, rather than this sort of thing. Please? -- To view, visit https://review.coreboot.org/c/coreboot/+/78913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1 Gerrit-Change-Number: 78913 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 21:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: payloads: Add uefistub payload
by David Milosevic (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Benjamin Doron, Martin L Roth, Maximilian Brune, Patrick Rudolph. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78913?usp=email ) Change subject: payloads: Add uefistub payload ...................................................................... Patch Set 4: (1 comment) File payloads/uefistub/src/arch/arm64/uefistub.ld: https://review.coreboot.org/c/coreboot/+/78913/comment/c326152a_720ad41c : PS4, Line 90: #ifdef CONFIG_EFI_FDT Use ```#if CONFIG_EFI_FDT == 1``` instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/78913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1 Gerrit-Change-Number: 78913 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 20:48:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 22: (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/84e66e64_6aef9eac : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > > Well, QEMU-SBSA is a rather simple example, with a homogenuous hierarchy […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 22 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 30 Nov 2023 20:30:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [UNTESTED] acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Cliff Huang, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79219?usp=email ) Change subject: [UNTESTED] acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC ...................................................................... Patch Set 1: (2 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/79219/comment/c6745a46_01c45c37 : PS1, Line 869: ACPI_DBG2_PORT_SERIAL_16550 > Maybe rename this one to `ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY` Done https://review.coreboot.org/c/coreboot/+/79219/comment/06e8d057_b9ef70c2 : PS1, Line 875: ACPI_DBG2_PORT_SERIAL_16550_GENERIC > I like this idea i like that idea too -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 20:22:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [UNTESTED] acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79219?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: [UNTESTED] acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC ...................................................................... [UNTESTED] acpi/acpi: add & use ACPI_DBG2_PORT_SERIAL_16550_GENERIC The Microsoft Debug Port Table 2 (DBG2) specification says that the serial port subtype 0x00 should only be used for I/O-mapped 16550 compatible UARTs. The subtype 0x12 is a superset of that, and supports specifying MMIO vs IO and the register access size via the generic address structure. Rename the subtype 0x00 definition to ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY and add the subtype 0x12 definition as new ACPI_DBG2_PORT_SERIAL_16550, so that the acpi_write_dbg2_uart function will write the correct subtype for the generic 16550 UART. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 --- M src/include/acpi/acpi.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79219/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816bb22e6f76e661c8b8e39a2a4cb83b0085acb5 Gerrit-Change-Number: 79219 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: inteltool/gpio_names/icelake.h: Add SPDX license header
by Felix Singer (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Martin L Roth, Nicholas Chin, Stefan Reinauer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78628?usp=email ) Change subject: inteltool/gpio_names/icelake.h: Add SPDX license header ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > Any reason not to combine all of the inteltool gpio_names SPDX header licenses into a single commit? +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a Gerrit-Change-Number: 78628 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 20:17:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2023