coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: inteltool/gpio_names/lewisburg.h: Add SPDX license header
by Alexander Couzens (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Nicholas Chin, Stefan Reinauer. Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78632?usp=email ) Change subject: inteltool/gpio_names/lewisburg.h: Add SPDX license header ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8e3f647c31a5facb062c372ada8c1f4a9228396 Gerrit-Change-Number: 78632 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 16:39:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Raul Rangel (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Bao Zheng, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Simon Glass, Tim Wawrzynczak, Zheng Bao. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... Patch Set 11: (1 comment) File src/soc/amd/common/block/acpi/tables.c: https://review.coreboot.org/c/coreboot/+/79174/comment/a0ddfb63_5dbdf21c : PS10, Line 15: current = acpi_16550_mmio32_write_dbg2_uart(rsdp, current, > Done Use a regular `if`, not a `#if` -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 30 Nov 2023 16:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main branch
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79315?usp=email ) Change subject: Update amd_blobs submodule to upstream main branch ...................................................................... Update amd_blobs submodule to upstream main branch Updating from commit id 68ebd4b567f4 (2023-11-27): PCO: Update ABL to version CABLRV21080200 to commit id eb91266f01db (2023-11-29): MDN: Update mendocino SMU to 90.43.0 This brings in 1 new commit: eb91266f01 MDN: Update mendocino SMU to 90.43.0 Change-Id: Iebc3d0ffe9874a84cac9cafc7b7b3514d251e4a5 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79315 Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Jon Murphy: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 68ebd4b..eb91266 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 68ebd4b567f467d2045c19251bb632fa337d99b6 +Subproject commit eb91266f01db2d276614dc20d8d0f857e6ffbf00 -- To view, visit https://review.coreboot.org/c/coreboot/+/79315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebc3d0ffe9874a84cac9cafc7b7b3514d251e4a5 Gerrit-Change-Number: 79315 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Trim GPIO comments
by Weimin Wu (Code Review) 30 Nov '23

30 Nov '23

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79321?usp=email ) Change subject: mb/google/nissa/var/anraggar: Trim GPIO comments ...................................................................... mb/google/nissa/var/anraggar: Trim GPIO comments Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/79321/1 diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index bc9e89d..8e0b76b 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -14,16 +14,16 @@ /* A18 : NC ==> HDMI_HPD_SRC*/ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD ==> NC */ + /* A20 : DDSP_HPD2 ==> NC */ PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), - /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P ==> NC */ + /* A21 : GPP_A21 ==> NC */ PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG), - /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N ==> NC */ + /* A22 : GPP_A22 ==> NC */ PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), - /* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA ==> MIPI_WCAM_SDA */ + /* B5 : I2C2_SDA ==> MIPI_WCAM_SDA */ PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), - /* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL ==> MIPI_WCAM_SCL */ + /* B6 : I2C2_SCL ==> MIPI_WCAM_SCL */ PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B11 : NC ==> EN_PP3300_WLAN_X*/ @@ -31,14 +31,14 @@ /* D6 : NC ==> WWAN_PWR_ENABLE */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ + /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG), - /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */ + /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), - /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP ==> GPP_E21_STRAP */ + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ @@ -52,22 +52,22 @@ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */ PAD_CFG_GPO(GPP_F18, 0, DEEP), - /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ + /* F23 : V1P05_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), - /* H12 : UART0_RTS# ==> SD_PERST_L ==> NC*/ + /* H12 : UART0_RTS# ==> NC*/ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), - /* H13 : UART0_CTS# ==> EN_PP3300_SD_X ==> NC */ + /* H13 : UART0_CTS# ==> NC */ PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R ==> NC */ + /* R6 : DMIC_CLK_A_1A ==> NC */ PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG), - /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA ==> NC */ + /* R7 : DMIC_DATA_1A ==> NC */ PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Gerrit-Change-Number: 79321 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/genoa: Implement romstage
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76514?usp=email ) Change subject: soc/amd/genoa: Implement romstage ...................................................................... soc/amd/genoa: Implement romstage The only thing romstage needs to do is find cbmem_top. TESTED: reaches ramstage. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76514 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/romstage.c 1 file changed, 9 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/genoa/romstage.c b/src/soc/amd/genoa/romstage.c index f4c5584..66a2140 100644 --- a/src/soc/amd/genoa/romstage.c +++ b/src/soc/amd/genoa/romstage.c @@ -1,10 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/post_codes.h> +#include <amdblocks/memmap.h> +#include <cbmem.h> +#include <program_loading.h> #include <romstage_common.h> -#include <halt.h> void __noreturn romstage_main(void) { - /* Needed for __noreturn */ - halt(); + post_code(POSTCODE_ROMSTAGE_MAIN); + + cbmem_initialize_empty(); + memmap_stash_early_dram_usage(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/76514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139 Gerrit-Change-Number: 76514 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: vendorcode/amd/opensil: Implement cbmem_top_chipset
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76513?usp=email ) Change subject: vendorcode/amd/opensil: Implement cbmem_top_chipset ...................................................................... vendorcode/amd/opensil: Implement cbmem_top_chipset Use an xPRF call to get the top of lower DRAM. Organize Makefile to keep romstage/ramstage components separate. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/vendorcode/amd/opensil/genoa_poc/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/romstage.c 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc index 5c7117a..c5742b5 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc +++ b/src/vendorcode/amd/opensil/genoa_poc/Makefile.inc @@ -3,8 +3,12 @@ CPPFLAGS_ramstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xUSL/FCH -I$(opensil_dir)/xUSL/FCH/Common -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF CPPFLAGS_romstage += -I$(opensil_dir)/Include -I$(opensil_dir)/xUSL -I$(opensil_dir)/xUSL/Include -I$(opensil_dir)/xSIM -I$(opensil_dir)/xPRF -ramstage-y += opensil_console.c romstage-y += opensil_console.c +romstage-y += romstage.c + +ramstage-y += opensil_console.c $(obj)/romstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas +$(obj)/romstage/vendorcode/amd/opensil/genoa_poc/romstage.o: CFLAGS_romstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas + $(obj)/ramstage/vendorcode/amd/opensil/genoa_poc/opensil_console.o: CFLAGS_ramstage += -D_MSC_EXTENSIONS=0 -DHAS_STRING_H=1 -Wno-unknown-pragmas diff --git a/src/vendorcode/amd/opensil/genoa_poc/romstage.c b/src/vendorcode/amd/opensil/genoa_poc/romstage.c new file mode 100644 index 0000000..e55ed1b --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include "opensil_console.h" +#include <xSIM-api.h> +#include <xPRF-api.h> + +uintptr_t cbmem_top_chipset(void) +{ + SilDebugSetup(HostDebugService); + uintptr_t top_mem = xPrfGetLowUsableDramAddress(0); + printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", top_mem); + + /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so + account for potentially ill aligned TOP_MEM. */ + if (CONFIG_SMM_TSEG_SIZE) { + top_mem -= CONFIG_SMM_TSEG_SIZE; + top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); + } + + return top_mem; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Gerrit-Change-Number: 76513 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79313?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id f2b01bf0: 2023-10-27 Julius Werner firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY to commit id ba7fd22d: 2023-11-27 Julius Werner Makefile: Always link libdl This brings in 54 new commits: ba7fd22d Makefile: Always link libdl 1b30d195 sign_official_build: sign_update_payload with pkcs11 ca7a1427 sign_firmware: support loem key config a9623573 sign_official_build: add keys to default key config d41497dc sign_official_build: support loem key config da2450db sign_official_build: support sign with .vbprik2 files ee326142 getversion: Make reproducible 8aaf9e32 futility: fix a typo in help message of `read` 9ce505f4 futility: Fix incorrect warning about signing length 23a0ce4e scripts: add lib/keycfg.sh 2e34330b Makefile: Fix firmware build for FIRMWARE_ARCH=arm64 fd5937d1 tests/futility/test_show_and_verify: Add test cases for invalid data key 00aa0626 futility/cmd_vbutil_kernel: Drop --pad option for --verify c661ab76 futility/cmd_show: Drop --pad option c70511d7 tests/futility/test_show_and_verify: Add test cases for kernel vblocks c9100f46 signer: Use compression flags stored in the metadata file f1f3076f vboot: Add vb_keyb_from_private_key c39a2fc1 host: support signing with pkcs11 key for vbprik2 c6d44076 vboot: merge reading function of vb2/vb21 private key 6b8e759f vboot: replace custom prefix "pkcs11" to "remote" 481440d0 futility: Prefer to flash over CCD instead of C2D2 1244c06f futility/cmd_dump_fmap: Print an error if FMAP header not found cab69289 futility/cmd_show: Fix parseable output for kernel preamble flags 71a03dc6 futility/cmd_show: Make preamble parseable output consistent bdac62a4 futility/cmd_show: Make 'show' return 0 for invalid kernel body 135df2d7 futility/cmd_show: Show parseable "keyblock::valid" for valid keyblock 37f37fcd futility/cmd_show: Fix output for firmware body signature 79c244ff tests/futility/test_show_and_verify: Add test cases for bios_brya_mp.bin d4b6560f signer: Update mkfs.erofs pcluster value to 32K f79a2432 futility/cmd_sign: Fix a space in usage text a307fcb5 futility: updater: rename --ccd to --ccd_without_servod 6b9f66d3 futility: updater: Fix malloc overflow due to broken keyblock a94a784c updater: update: Support multiple Servos without --servo_port 25875bef tests/futility: Add test cases for VBOOT_CBFS_INTEGRATION 5f8e3973 futility/cmd_show: Fix typo "metatadata" 9d30a01f futility: Trim trailing spaces in kernel config c59794a6 sign_uefi: Support signing via pkcs11 68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI 6b9d624b sign_uefi: Pass each key path separately 483f65e4 sign_official_build.sh: properly show errors on loem issues 516ee7bc sign_uefi: Use named args instead of positional 0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder 46f5aab8 image_signing: support multiple release names f13af139 sign_official_build: Sudo invocation within bits of android signing 3f165374 futility: updater: Add optional serial number argument to --ccd 64379cc6 sign_official_build: add --debug flag 7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc 0e27cdff vboot_reference-sys: Add vboot_host.h 2c82e73c Override use_apksigner FLAGS b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK 0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin 68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh 8daf1474 tests/futility: Move 'futility show' tests to a separate file 34190e3d futility: Exit with error when metadata hash verification not supported 967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size() Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79313 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Uwe Poeche: Looks good to me, but someone else must approve diff --git a/3rdparty/vboot b/3rdparty/vboot index c59794a..ba7fd22 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit c59794a6e939af42f36086d5fd656ee7496eb4b6 +Subproject commit ba7fd22d3dd659b3ab42ad66f22169a6ce0f4dfe -- To view, visit https://review.coreboot.org/c/coreboot/+/79313?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58b231d53f433a396b1ea8cd4e0ddc49a310e385 Gerrit-Change-Number: 79313 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: Update arm-trusted-firmware submodule to upstream master
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79333?usp=email ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 88b2d8134: 2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration) to commit id e7486343d: 2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration) This brings in 451 new commits. Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79333 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 88b2d81..e748634 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 88b2d81345dfd84902aae586a743d00ac5df2f48 +Subproject commit e7486343d46a0d60047233adfd8a64436bbac1fd -- To view, visit https://review.coreboot.org/c/coreboot/+/79333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f Gerrit-Change-Number: 79333 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/corsola: Use fw_config to differentiate audio amps
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79309?usp=email ) Change subject: mb/google/corsola: Use fw_config to differentiate audio amps ...................................................................... mb/google/corsola: Use fw_config to differentiate audio amps Use fw_config to differentiate audio amps instead of the kconfig option. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309 Reviewed-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/corsola/mainboard.c 2 files changed, 11 insertions(+), 3 deletions(-) Approvals: Ruihai Zhou: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 0e8bb91..300ba7b 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,4 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +fw_config + field AUDIO_AMP 28 29 + option AMP_ALC1019 0 + option AMP_ALC5645 1 + end +end chip soc/mediatek/mt8186 device cpu_cluster 0 on end diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a6659a5..37f3a70 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> +#include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> #include <soc/i2c.h> @@ -51,10 +52,11 @@ setup_usb_host(); - if (CONFIG(BOARD_GOOGLE_CHINCHOU)) - configure_alc5645(); - else + if (!fw_config_is_provisioned() || + fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019))) configure_alc1019(); + else if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC5645))) + configure_alc5645(); if (spm_init()) printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/79309?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Gerrit-Change-Number: 79309 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Add LTE only daughterboard support
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79297?usp=email ) Change subject: mb/google/nissa/var/quandiso: Add LTE only daughterboard support ...................................................................... mb/google/nissa/var/quandiso: Add LTE only daughterboard support Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Shawn Ku <shawnku(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/quandiso/fw_config.c M src/mainboard/google/brya/variants/quandiso/overridetree.cb 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Shawn Ku: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/quandiso/fw_config.c b/src/mainboard/google/brya/variants/quandiso/fw_config.c index c5ac0d2..dc286a8 100644 --- a/src/mainboard/google/brya/variants/quandiso/fw_config.c +++ b/src/mainboard/google/brya/variants/quandiso/fw_config.c @@ -75,7 +75,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && + !fw_config_probe(FW_CONFIG(DB_USB, DB_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 29a4cee..205fd2b 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -2,7 +2,7 @@ field DB_USB 0 1 option DB_NONE 0 option DB_1C_1A 1 - option DB_1C 2 + option DB_LTE 2 option DB_1C_LTE 3 end field WIFI_SAR_ID 2 3 @@ -333,6 +333,7 @@ register "reg_adv_ctrl19" = "0xf0" register "reg_adv_ctrl20" = "0xf0" device i2c 28 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end @@ -444,7 +445,6 @@ use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -468,7 +468,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -492,7 +491,6 @@ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on probe DB_USB DB_1C_1A - probe DB_USB DB_1C probe DB_USB DB_1C_LTE end end @@ -565,6 +563,7 @@ register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port2 on + probe DB_USB DB_LTE probe DB_USB DB_1C_LTE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Gerrit-Change-Number: 79297 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2023