coreboot-gerrit November 2023

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Change in coreboot[master]: nb/intel/sandybridge: Refine power-down mode logic
by Angel Pons (Code Review) 04 Jan '24

04 Jan '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47746 ) Change subject: nb/intel/sandybridge: Refine power-down mode logic ...................................................................... nb/intel/sandybridge: Refine power-down mode logic When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 41 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47746/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..9cd522f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -99,6 +99,15 @@ hex default 0x0 +config RAMINIT_ALWAYS_ALLOW_DLL_OFF + bool "Also enable memory DLL-off mode on desktops and servers" + default n + help + If enabled, allow enabling DLL-off mode for platforms other than + mobile. Saves power at the expense of higher exit latencies. Has + no effect on mobile platforms, where DLL-off is always allowed. + Power down is disabled for stability when running at high clocks. + config RAMINIT_ENABLE_ECC bool "Enable ECC if supported" default y diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b06734c..d533ca8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -688,11 +688,29 @@ iosav_run_once(channel); } +/* Obtain optimal power down mode for current configuration */ +static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +{ + if (ctrl->tXP > 8) + return PDM_NONE; + + if (ctrl->tXPDLL > 32) + return PDM_PPD; + + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) + return PDM_DLL_OFF; + + return PDM_APD_PPD; +} + static u32 make_mr0(ramctr_timing *ctrl, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; + + const enum pdwm_mode power_down = get_power_down_mode(ctrl); + + const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { @@ -712,8 +730,8 @@ mr0reg |= (mch_cas & 0xe) << 3; mr0reg |= mch_wr << 9; - /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg |= !is_mobile << 12; + /* Precharge PD - Use slow exit when DLL-off is used - mostly power-saving feature */ + mr0reg |= !slow_exit << 12; return mr0reg; } @@ -2830,8 +2848,6 @@ /* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { - const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; - int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; @@ -2848,12 +2864,8 @@ MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; } - if (is_mobile) - /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; - else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; + /* 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; FOR_ALL_CHANNELS MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 050aa70..80d3074 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -273,6 +273,15 @@ */ #define MRC_CACHE_VERSION 5 +enum pdwm_mode { + PDM_NONE = 0, + PDM_APD = 1, + PDM_PPD = 2, + PDM_APD_PPD = 3, + PDM_DLL_OFF = 6, + PDM_APD_DLL_OFF = 7, +}; + typedef struct odtmap_st { u16 rttwr; u16 rttnom; -- To view, visit https://review.coreboot.org/c/coreboot/+/47746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Gerrit-Change-Number: 47746 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

[L] Change in coreboot[main]: mb/google/rex/variants/deku: Add GPIO configuration
by Felix Held (Code Review) 30 Nov '23

30 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78960?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex/variants/deku: Add GPIO configuration ...................................................................... mb/google/rex/variants/deku: Add GPIO configuration Based on Platform Mapping Document for Deku (go/cros-deku-mapping) from Nov 8, 2023 (Rev 0.4) BUG=b:305793886 TEST=WIP, not tested yet Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d Signed-off-by: Eran Mitrani <mitrani(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/deku/gpio.c 1 file changed, 416 insertions(+), 11 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index b6e346f..324c236 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -6,25 +6,430 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPP_A00 : [] ==> ESPI_SOC_D0_R */ + PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A01 : [] ==> ESPI_SOC_D1_R */ + PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A02 : [] ==> ESPI_SOC_D2_R */ + PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A03 : [] ==> ESPI_SOC_D3_R */ + PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A04 : [] ==> ESPI_SOC_CS_L */ + PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A05 : [] ==> ESPI_SOC_CLK_R */ + PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A06 : [] ==> ESPI_SOC_RST_L */ + PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A11 : [] ==> LAN0_ISOLATE_R_ODL */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* GPP_A12 : [] ==> LAN1_ISOLATE_R_ODL */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* GPP_A13 : net NC is not present in the given design */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 : net NC is not present in the given design */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 : net NC is not present in the given design */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */ + PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), + /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_A18 : net NC is not present in the given design */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [] ==> EN_PWR_SSD_OD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), + /* GPP_A21 : [] ==> SOC_GPP_A21 */ + PAD_NC(GPP_A21, NONE), + + /* GPP_B00 : net NC is not present in the given design */ + PAD_NC(GPP_B00, NONE), + /* GPP_B01 : [] ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_B01, 1, DEEP), + /* GPP_B02 : [] ==> SOC_ISH_I2C_SDA */ + PAD_CFG_NF_LOCK(GPP_B02, NONE, NF3, LOCK_CONFIG), + /* GPP_B03 : [] ==> SOC_ISH_I2C_SCL */ + PAD_CFG_NF_LOCK(GPP_B03, NONE, NF3, LOCK_CONFIG), + /* GPP_B04 : [GPP_B04_STRAP] ==> Component NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05 : net NC is not present in the given design */ + PAD_NC(GPP_B05, NONE), + /* GPP_B06 : net NC is not present in the given design */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07 : IOEX_INT_ODL */ + PAD_CFG_GPI(GPP_B07, NONE, DEEP), + /* GPP_B08 : [] ==> PWM_BUZZER */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + /* GPP_B09 : net NC is not present in the given design */ + PAD_NC(GPP_B09, NONE), + /* GPP_B10 : [] ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), + /* GPP_B11 : net NC is not present in the given design */ + PAD_NC(GPP_B11, NONE), + /* GPP_B12 : [] ==> SLP_S0_R_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 : [] ==> PLT_PCIE_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 : [GPP_B14_STRAP] ==> Component NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15 : [] ==> USB_A_OC_ODL */ + PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), + /* GPP_B16 : net NC is not present in the given design */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17 : net NC is not present in the given design */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), + /* GPP_B20 : net NC is not present in the given design */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21 : net NC is not present in the given design */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22 : [] ==> USB_C_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 : net NC is not present in the given design */ + PAD_NC(GPP_B23, NONE), + + /* GPP_C00 : net NC is not present in the given design */ + PAD_NC(GPP_C00, NONE), + /* GPP_C01 : net NC is not present in the given design */ + PAD_NC(GPP_C01, NONE), + /* GPP_C02 : [GPP_C02_STRAP] ==> Component NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03 : net NC is not present in the given design */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04 : net NC is not present in the given design */ + PAD_NC(GPP_C04, NONE), + /* GPP_C05 : [GPP_C05_STRAP] ==> Component NC */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06 : net NC is not present in the given design */ + PAD_NC(GPP_C06, NONE), + /* GPP_C07 : net NC is not present in the given design */ + PAD_NC(GPP_C07, NONE), + /* GPP_C08 : [] ==> SOCHOT_ODL */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), + /* GPP_C09 : [] ==> MISC_SYNC_OD */ + PAD_CFG_GPI(GPP_C09, NONE, DEEP), + /* GPP_C10 : net NC is not present in the given design*/ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 : [] ==> LAN1_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 : net NC is not present in the given design */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 : [] ==> LAN0_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG), + /* GPP_C15 : [GPP_C15_STRAP] ==> Component NC */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 : [] ==> USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 : [] ==> USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 : [] ==> USB_C2_LSX_TX */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19 : [] ==> USB_C2_LSX_RX */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20 : [] ==> USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21 : [] ==> USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22 : [] ==> USB_C3_LSX_TX */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* GPP_C23 : [] ==> USB_C3_LSX_RX */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + + /* GPP_D00 : net NC is not present in the given design */ + PAD_NC(GPP_D00, NONE), + /* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PLTRST, LEVEL, INVERT), + /* GPP_D02 : [] ==> LAN1_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), + /* GPP_D03 : net NC is not present in the given design */ + PAD_NC(GPP_D03, NONE), + /* GPP_D04 : net NC is not present in the given design */ + PAD_NC(GPP_D04, NONE), + /* GPP_D05 : [] ==> UART_DBG_TX_ISH_RX */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06 : [] ==> UART_ISH_TX_DBG_RX */ + PAD_NC(GPP_D06, NONE), + /* GPP_D07 : [] ==> SOC_GPP_D07 */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08 : net NC is not present in the given design */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09 : net NC is not present in the given design */ + PAD_NC(GPP_D09, NONE), + /* GPP_D10 : net NC is not present in the given design */ + PAD_NC(GPP_D10, NONE), + /* GPP_D11 : net NC is not present in the given design */ + PAD_NC(GPP_D11, NONE), + /* GPP_D12 : [GPP_D12_STRAP] ==> Component NC */ + PAD_NC(GPP_D12, NONE), + /* GPP_D13 : net NC is not present in the given design */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 : net NC is not present in the given design */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15 : net NC is not present in the given design */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 : net NC is not present in the given design */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17 : net NC is not present in the given design */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18 : net NC is not present in the given design */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 : [] ==> SSD_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D20 : [] ==> LAN0_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 : [] ==> WLAN_PCIE_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 : [] ==> SOC_DBG_BPKI3C_SDA */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 : [] ==> SOC_DBG_BPKI3C_SCL */ + PAD_NC(GPP_D23, NONE), + + /* GPP_E00 : net NC is not present in the given design */ + PAD_NC(GPP_E00, NONE), + /* GPP_E01 : [] ==> MEM_STRAP_2 */ + PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), + /* GPP_E02 : [] ==> MEM_STRAP_1 */ + PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E04 : [] ==> LAN0_PCIE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : net NC is not present in the given design */ + PAD_NC(GPP_E07, NONE), + /* GPP_E08 : [] ==> SOC_GPP_E08 */ + PAD_NC(GPP_E08, NONE), + /* GPP_E09 : [] ==> USB_C_OC_ODL */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), + /* GPP_E10 : net NC is not present in the given design */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11 : [] ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* GPP_E12 : [] ==> MEM_STRAP_3 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* GPP_E14 : net NC is not present in the given design */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15 : [] ==> SOC_GPP_E15 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16 : [] ==> GPP_E16_ISH_GP10 */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17 : net NC is not present in the given design */ + PAD_NC(GPP_E17, NONE), + /* GPP_E22 : net NC is not present in the given design */ + PAD_NC(GPP_E22, NONE), + + /* GPP_F00 : [] ==> CNV_BRI_DT_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 : [] ==> WLAN_CNVI_BRI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 : [] ==> CNV_RGI_DT_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 : [] ==> WLAN_CNVI_RGI_RSP */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 : [] ==> WLAN_CNVI_RF_RST_L */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 : [] ==> WLAN_CNVI_CLKREQ0 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 : [] ==> WLAN_COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07 : net NC is not present in the given design */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08 : [] ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09 : net NC is not present in the given design */ + PAD_NC(GPP_F09, NONE), + /* GPP_F10 : net NC is not present in the given design */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11 : net NC is not present in the given design */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 : net NC is not present in the given design */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 : net NC is not present in the given design */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14 : net NC is not present in the given design */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 : net NC is not present in the given design */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 : net NC is not present in the given design */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 : net NC is not present in the given design */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18 : net NC is not present in the given design */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 : [GPP_F19_STRAP] ==> Component NC */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* GPP_F20 : [GPP_F20_STRAP] ==> Component NC */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* GPP_F21 : [GPP_F21_STRAP] ==> Component NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 : [] ==> GPP_F22_ISH_GP8A */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 : [] ==> TP_SOC_ISH_MCF_INT_L */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H04 : [] ==> WLAN_COEX1 */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), + /* GPP_H05 : [] ==> WLAN_COEX2 */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), + /* GPP_H06 : net NC is not present in the given design */ + PAD_NC(GPP_H06, NONE), + /* GPP_H07 : net NC is not present in the given design */ + PAD_NC(GPP_H07, NONE), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + /* GPP_H11 : net NC is not present in the given design */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13 : [] ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : [] ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H15 : net NC is not present in the given design */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16 : net NC is not present in the given design */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17 : net NC is not present in the given design */ + PAD_NC(GPP_H17, NONE), + /* GPP_H19 : [] ==> I2C_IOEX_SDA */ + PAD_CFG_NF_LOCK(GPP_H19, NONE, NF1, LOCK_CONFIG), + /* GPP_H20 : [] ==> I2C_IOEX_SCL */ + PAD_CFG_NF_LOCK(GPP_H20, NONE, NF1, LOCK_CONFIG), + /* GPP_H21 : net NC is not present in the given design */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22 : net NC is not present in the given design */ + PAD_NC(GPP_H22, NONE), + + /* GPP_S00 : net NC is not present in the given design */ + PAD_NC(GPP_S00, NONE), + /* GPP_S01 : net NC is not present in the given design */ + PAD_NC(GPP_S01, NONE), + /* GPP_S02 : net NC is not present in the given design */ + PAD_NC(GPP_S02, NONE), + /* GPP_S03 : net NC is not present in the given design */ + PAD_NC(GPP_S03, NONE), + /* GPP_S04 : net NC is not present in the given design */ + PAD_NC(GPP_S04, NONE), + /* GPP_S05 : net NC is not present in the given design */ + PAD_NC(GPP_S05, NONE), + /* GPP_S06 : net NC is not present in the given design */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07 : net NC is not present in the given design */ + PAD_NC(GPP_S07, NONE), + + /* GPP_V00 : [] ==> BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01 : [] ==> ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04 : [] ==> SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 : [] ==> SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 : [] ==> SLP_A_L */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V08 : [] ==> SOC_SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 : [] ==> SLP_WLAN_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 : [] ==> SLP_S5_L */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 : [] ==> EC_SOC_REC_SWITCH_ODL */ + PAD_CFG_GPI_LOCK(GPP_V11, NONE, LOCK_CONFIG), + /* GPP_V12 : [] ==> SLP_LAN_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V14 : [] ==> SOC_WAKE_L */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V22 : net NC is not present in the given design */ + PAD_NC(GPP_V22, NONE), + /* GPP_V23 : net NC is not present in the given design */ + PAD_NC(GPP_V23, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), + + /* GPP_C13 : [] ==> LAN0_PERST_L */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + + /* GPP_D02 : [] ==> LAN1_PERST_L */ + PAD_CFG_GPO(GPP_D02, 0, DEEP), + + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_C13 : [] ==> LAN0_PERST_L */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + + /* GPP_D02 : [] ==> LAN1_PERST_L */ + PAD_CFG_GPO(GPP_D02, 0, DEEP), +}; + const struct pad_config *variant_gpio_table(size_t *num) { - *num = 0; - return NULL; + + *num = ARRAY_SIZE(gpio_table); + return gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; } -static const struct cros_gpio cros_gpios[] = { -}; - -DECLARE_CROS_GPIOS(cros_gpios); - const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); -- To view, visit https://review.coreboot.org/c/coreboot/+/78960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d Gerrit-Change-Number: 78960 Gerrit-PatchSet: 8 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Karthik Ramasubramanian (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Ivy Jian, Nick Vaccaro, Shelley Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/gpio.c: https://review.coreboot.org/c/coreboot/+/79355/comment/5523b359_b273f4cb : PS3, Line 404: const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) : { I am afraid the weak override here will be overridden by the table here - https://review.coreboot.org/c/coreboot/+/79295/4/src/mainboard/google/brox/…. It makes sense to move this config over to the other table. -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 23:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 30 Nov '23

30 Nov '23

Shelley Chen has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP & MEM_CH_SEL gpios for use in romstage. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c 2 files changed, 58 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79355/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Enable LAN0, LAN1
by Paul Menzel (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79292?usp=email ) Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1 ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Gerrit-Change-Number: 79292 Gerrit-PatchSet: 8 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 22:20:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)
by Julius Werner (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Jérémy Compostella, Simon Glass. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79317?usp=email ) Change subject: Introduce a coreboot Control Block (CCB) ...................................................................... Patch Set 2: Code-Review-2 (5 comments) Patchset: PS2: Sorry but I do not understand why we are suddenly proceeding to implementation with this. Everywhere this was discussed before in both the leadership meetings and on the mailing list, you have repeatedly received feedback from multiple people that we shouldn't add yet another configuration backend and instead just add serial control to any of the existing ones. I feel like you have consistently just ignored that feedback and kept bringing up the same proposal again and again without even really engaging the objections. I still maintain that this is not good for coreboot, the added complexity to firmware layout and cbfstool is in no way worth the benefit, this interacts badly with edge cases on certain platforms or other feature configurations (e.g. verification), and we should focus on consolidating the existing configuration backends we have rather than adding yet another one that is super narrow and will in practice only be used for a single thing (especially when it is so invasive). People have proposed plenty of alternatives that could be used for post-build serial control including option table (CMOS), VPD, FW_CONFIG (CBI) and a CBFS file — in fact, the option table mechanism for this has always existed, and for CBFS files we have an almost finished patch series which would just need to be rebased and cleaned up (CB:45208). The only real argument for adding all this extra stuff instead is to control serial output in a very narrow time window in the early bootblock before CBFS access is available, and it seems incredibly unlikely that something goes wrong in that tiny early window during a development phase where you don't still have serial console enabled by default anyway. If you are adamant to keep pushing this approach then I guess maybe we'll need to have another big discussion and force a decision in the leadership meeting or something. But I don't think this should be decided by just continuously pushing the same thing until the people with objections get tired or happen to be on vacation. So I'll -2 this until I'm convinced there is a majority in favor. File Documentation/technotes/ccb.md: https://review.coreboot.org/c/coreboot/+/79317/comment/d2670d71_88bd445f : PS2, Line 79: Some boards used a signed bootblock which cannot easily be modified after : building, since it requires resigning parts of the image. To address this, the : CCB could be stored in the romstage instead. This means it is unable to affect : the operation of bootblock, of course. This could be controlled by a new : ROMSTAGE_CCB option. This would literally invalidate the only reason you've used to justify this approach (over other post-build configuration options like CBFS files). File src/arch/x86/car.ld: https://review.coreboot.org/c/coreboot/+/79317/comment/53d43d0b_7ad2e5f2 : PS2, Line 45: CCB(., 0x10) This file only affects x86 devices (excluding AMD). Expanding this to other platforms puts the burden of finding room for this in the memlayout (and remembering to do so) on every single platform owner, which will lead to a fragmented landscape where only a random selection of platforms supports this. That's another good reason to reject this solution over the alternatives that don't need to pass the setting forward between stages. File src/arch/x86/postcar.c: https://review.coreboot.org/c/coreboot/+/79317/comment/c2ec411e_cea94f82 : PS2, Line 33: console_init(); Moving console_init() down here makes it impossible to debug CBMEM initialization handlers, of which there are many and which can sometimes be non-trivial. File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/79317/comment/dc0e3bfe_6f107e3b : PS2, Line 433: default y Any feature for runtime control of console behavior should probably be based on loglevel as it was suggested back in CB:45208, not create yet another orthogonal setting. -- To view, visit https://review.coreboot.org/c/coreboot/+/79317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f6a7a3e136067859e4e8c2043cf39f2a1771c0f Gerrit-Change-Number: 79317 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Comment-Date: Thu, 30 Nov 2023 22:18:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Nico Huber (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 22: Code-Review+1 (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/21a942a0_5df9e9f3 : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > Done Sorry for the delay. We'll have to see how this works once there are real-hardware ports, I guess. And then we might have to adjust. But nothing to do right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 22 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Thu, 30 Nov 2023 22:17:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 30 Nov '23

30 Nov '23

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP gpios in for romstage. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c 2 files changed, 56 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79355/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brox: Fix memory config
by Shelley Chen (Code Review) 30 Nov '23

30 Nov '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email ) Change subject: mb/google/brox: Fix memory config ...................................................................... mb/google/brox: Fix memory config Fix up the memory config for brox based on the schematics. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/memory.c 2 files changed, 56 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79355/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index daf1b96..92fdecc 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -381,21 +381,33 @@ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* Initialize MEM_STRAPs for memory training in romstage */ + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), +}; + const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } +const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_WEAK_CROS_GPIOS(cros_gpios); - -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c index bcad9b4..25f3092 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c @@ -5,65 +5,64 @@ #include <gpio.h> static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP4X, + .type = MEM_TYPE_LP5X, - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = {40, 30, 30, 30, 30}, - }, + /* Leave Rcomp unspecified to use the FSP optimized defaults */ /* DQ byte map */ .lpx_dq_map = { .ddr0 = { - .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, - .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, }, + .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, }, }, .ddr1 = { - .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr2 = { - .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, - .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, }, + .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, }, }, .ddr3 = { - .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, - .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, }, + .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, }, }, .ddr4 = { - .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, - .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, }, + .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, }, }, .ddr5 = { - .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, - .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, }, .ddr6 = { - .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, - .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, }, + .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, }, }, .ddr7 = { - .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, - .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, }, + .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, }, }, }, /* DQS CPU<>DRAM map */ .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .ect = 1, /* Enable Early Command Training */ + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + }; const struct mb_cfg *__weak variant_memory_params(void) @@ -75,16 +74,16 @@ { /* * Memory configuration board straps - * GPIO_MEM_CONFIG_0 GPP_E11 - * GPIO_MEM_CONFIG_1 GPP_E2 - * GPIO_MEM_CONFIG_2 GPP_E1 - * GPIO_MEM_CONFIG_3 GPP_E12 + * GPIO_MEM_CONFIG_0 GPP_E15 + * GPIO_MEM_CONFIG_1 GPP_E12 + * GPIO_MEM_CONFIG_2 GPP_E13 + * GPIO_MEM_CONFIG_3 GPP_E10 */ gpio_t spd_gpios[] = { - GPP_E11, - GPP_E2, - GPP_E1, + GPP_E15, GPP_E12, + GPP_E13, + GPP_E10, }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); @@ -92,8 +91,8 @@ bool __weak variant_is_half_populated(void) { - /* GPIO_MEM_CH_SEL GPP_E13 */ - return gpio_get(GPP_E13); + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); } void __weak variant_get_spd_info(struct mem_spd *spd_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/79355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Gerrit-Change-Number: 79355 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd: Add DBG2 ACPI table
by Simon Glass (Code Review) 30 Nov '23

30 Nov '23

Attention is currently required from: Bao Zheng, Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, Zheng Bao. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd: Add DBG2 ACPI table ...................................................................... Patch Set 11: Code-Review+1 (1 comment) Patchset: PS11: LGTM. I was hoping to test this today but did not get time. You can try it on skyrim using altfw. Make sure you sync to the latest source. Use the *non-serial* image. Then if U-Boot shows a serial console on boot, all is well. Thank you for doing this! -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 30 Nov 2023 21:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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