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Change subject: mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/quandiso/fw_config.c:
https://review.coreboot.org/c/coreboot/+/79173/comment/078ee750_cfecb20e :
PS4, Line 76: static const struct pad_config disable_usbc1_pins[] = {
> I only found aux pin here register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, . […]
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/src/…
From nissa baseboard gpio.c and quandiso gpio table, A21 and A22 are USB_C1_AUX_DC for nivviks, yavi* series and quandiso.
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Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79222?usp=email )
Change subject: mb/asus/p8z77-m: Properly configure early serial
......................................................................
mb/asus/p8z77-m: Properly configure early serial
Board was not producing serial output until well into ramstage.
To fix, select SUPERIO_NUVOTON_COMMON_COM_A Kconfig to tell
nuvoton_enable_serial() to route serial port A signals to the outside,
not GPIO8x.
TEST=Full native raminit debug log received over serial by minicom.
Change-Id: I376a79dd76ffa5f4d47e7c0cb53680e173e1ad78
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/79222/1
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 277fe40..e278b56 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -54,6 +54,7 @@
select BOARD_ROMSIZE_KB_8192
select MEMORY_MAPPED_TPM
select SUPERIO_NUVOTON_NCT6779D
+ select SUPERIO_NUVOTON_COMMON_COM_A
if BOARD_ASUS_P8X7X_SERIES
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Hello Angel Pons, Patrick Rudolph, Vlado Cibic, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73693?usp=email
to look at the new patch set (#10).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asus/p8z77-m_pro: Drop useless early init code
......................................................................
mb/asus/p8z77-m_pro: Drop useless early init code
Drop code that puts Super I/O into config mode, select serial device,
then leave config mode right away having done nothing.
I'll also take this chance to revise its #includes based on
include-what-you-use results.
Change-Id: I304fc1610740375b59121b6b8784122440795838
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
1 file changed, 1 insertion(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/73693/10
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Change subject: mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/quandiso/fw_config.c:
https://review.coreboot.org/c/coreboot/+/79173/comment/a1df9dc6_9c553b58 :
PS4, Line 76: static const struct pad_config disable_usbc1_pins[] = {
I only found aux pin here register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" why A21 a22?
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Change subject: mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboard
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Hi @ericllai@google.com,
Can you help to review this commit?
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Change subject: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hmmm, do you have a link to these sandybridge changes? I'd like to see these review comments
See the discussions around CB:76965.
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Change subject: libpayload: Fix the stack and data labels
......................................................................
Patch Set 3:
(2 comments)
File payloads/libpayload/arch/arm/libpayload.ldscript:
https://review.coreboot.org/c/coreboot/+/79144/comment/0e83aa12_4dab63a8 :
PS3, Line 50: *(.rodata.*)
Can we just add `_text`/`_etext`, `_rodata`/`_erodata` and `_bss`/`_ebss` everywhere here as well for consistency?
https://review.coreboot.org/c/coreboot/+/79144/comment/d7e88f1c_5a5b4d42 :
PS3, Line 77: _stack = .;
Be careful, these are actually used, so you need to fix the references in the relevant assembly files as well (the three `arch/<arch>/head.S`).
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Change subject: libpayload: Move ttb_buffer to a standalone section
......................................................................
Patch Set 8: Code-Review+2
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Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78866?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: vboot: Add catchall recovery reason for unspecified phase 4 errors
......................................................................
vboot: Add catchall recovery reason for unspecified phase 4 errors
The code for "phase 4" of firmware verification currently only sets a
recovery reason when there's an actual hash mismatch detected in
vb2api_check_hash_get_digest(). This is the most likely way how this
section of code can fail but not the only one. If any other unexpected
issue occurs, we should still set a recovery reason rather than just
reboot and risk an infinite boot loop.
This patch adds a catchall recovery reason for any error code that falls
out of this block of code. If a more specific recovery reason had
already been set beforehand, we'll continue to use that -- if not, we'll
set VB2_RECOVERY_FW_GET_FW_BODY.
Change-Id: If00f00f00f00aa113e0325aad58d367f244aca49
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78866
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/security/vboot/vboot_logic.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 11983b9..93a188c 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -374,7 +374,7 @@
}
if (rv)
- vboot_save_and_reboot(ctx, rv);
+ vboot_fail_and_reboot(ctx, VB2_RECOVERY_FW_GET_FW_BODY, rv);
vboot_save_data(ctx);
/* Only extend PCRs once on boot. */
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