coreboot-gerrit November 2023

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[S] Change in coreboot[main]: acpi: Enable 64bit ECAM resource
by Tim Wawrzynczak (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Naresh Solanki, Nico Huber, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79096?usp=email ) Change subject: acpi: Enable 64bit ECAM resource ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08 Gerrit-Change-Number: 79096 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 22 Nov 2023 17:50:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: acpigen.c: Add resource consumer functions for mmio
by Tim Wawrzynczak (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Felix Held, Lance Zhao, Nico Huber. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79217?usp=email ) Change subject: acpigen.c: Add resource consumer functions for mmio ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79217?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e Gerrit-Change-Number: 79217 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Nov 2023 17:08:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: util/crossgcc: Update GCC from 11.3 to 12.2
by Felix Singer (Code Review) 22 Nov '23

22 Nov '23

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/66922?usp=email ) Change subject: util/crossgcc: Update GCC from 11.3 to 12.2 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/66922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09 Gerrit-Change-Number: 66922 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: abandon

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[L] Change in coreboot[main]: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
by Felix Singer (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Elyes Haouas, Lennart Eichhorn, Nico Huber, Patrick Georgi. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70771?usp=email ) Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 ...................................................................... Patch Set 29: (1 comment) File util/crossgcc/patches/gcc-11.4.0_rv32iafc.patch: PS29: > I can't find `iafc` in the 13.2 sources. […] Good question, I can't tell. I will try to put it back. -- To view, visit https://review.coreboot.org/c/coreboot/+/70771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 29 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 22 Nov 2023 16:13:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
by Matt DeVillier (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Mark Hasemeyer, Matt DeVillier, Raul Rangel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79155?usp=email ) Change subject: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Gerrit-Change-Number: 79155 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 Nov 2023 15:26:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: add I2C support
by Felix Held (Code Review) 22 Nov '23

22 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78900?usp=email ) Change subject: soc/amd/genoa: add I2C support ...................................................................... soc/amd/genoa: add I2C support The Genoa SoC has 6 I2C controllers. In order to support those, select SOC_AMD_COMMON_BLOCK_I2C and implement the SoC-specific functions and data structures needed by the common AMD I2C code. Since the common AMD I2C code also reports if the controller is enabled or not in the SSDT, change the corresponding DSDT code to use this information. In this patch the I2C pad control registers don't get configured by coreboot yet and we rely on ABL already having those set up correctly which seems to be an assumption that the reference firmware is making too. PPR #55901 Rev 0.26 was used as a reference for the I2C controllers and the GPIO pins being used. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/acpi/mmio.asl M src/soc/amd/genoa/chip.h M src/soc/amd/genoa/chipset.cb A src/soc/amd/genoa/i2c.c A src/soc/amd/genoa/include/soc/i2c.h M src/soc/amd/genoa/include/soc/iomap.h 8 files changed, 130 insertions(+), 12 deletions(-) Approvals: Varshit Pandya: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 210b3e5..cbf0ddd 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -20,6 +20,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX @@ -43,6 +44,10 @@ string default "soc/amd/genoa/chipset.cb" +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 150 + config EARLY_RESERVED_DRAM_BASE hex default 0x7000000 diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 33a4061..4b47886 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -5,6 +5,7 @@ all-y += reset.c all-y += config.c all-y += gpio.c +all-y += i2c.c all-y += uart.c bootblock-y += early_fch.c diff --git a/src/soc/amd/genoa/acpi/mmio.asl b/src/soc/amd/genoa/acpi/mmio.asl index 8ef61a7..9b5e1d2 100644 --- a/src/soc/amd/genoa/acpi/mmio.asl +++ b/src/soc/amd/genoa/acpi/mmio.asl @@ -195,9 +195,10 @@ } } + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0) @@ -231,9 +232,10 @@ } } + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0) @@ -267,9 +269,10 @@ } } + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0) @@ -303,9 +306,11 @@ Return (Local0) } } + + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) @@ -339,9 +344,11 @@ Return (Local0) } } + + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C4, 0) @@ -375,9 +382,11 @@ Return (Local0) } } + + Name (STAT, 0x0) Method (_STA, 0x0, NotSerialized) { - Return (0x0F) + Return (STAT) } AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0) diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h index 9168586..bca40af 100644 --- a/src/soc/amd/genoa/chip.h +++ b/src/soc/amd/genoa/chip.h @@ -4,9 +4,16 @@ #define __GENOA_CHIP_H__ #include <amdblocks/chip.h> +#include <amdblocks/i2c.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/iomap.h> +#include <types.h> struct soc_amd_genoa_config { struct soc_amd_common_config common_config; + + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; }; #endif diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 58c1156..0f543e7 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -207,12 +207,12 @@ end end - device mmio 0xfedc2000 alias i2c_0 off end - device mmio 0xfedc3000 alias i2c_1 off end - device mmio 0xfedc4000 alias i2c_2 off end - device mmio 0xfedc5000 alias i2c_3 off end - device mmio 0xfedc6000 alias i2c_4 off end - device mmio 0xfedcb000 alias i2c_5 off end + device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedc6000 alias i2c_4 off ops soc_amd_i2c_mmio_ops end + device mmio 0xfedcb000 alias i2c_5 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end diff --git a/src/soc/amd/genoa/i2c.c b/src/soc/amd/genoa/i2c.c new file mode 100644 index 0000000..76c1049 --- /dev/null +++ b/src/soc/amd/genoa/i2c.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <soc/i2c.h> +#include <soc/southbridge.h> +#include "chip.h" + +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), + I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL), + I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL), +}; + +static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }, + { I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" }, + { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" } +}; + +void reset_i2c_peripherals(void) +{ + const struct soc_amd_genoa_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + /* TODO: write I2C pad control registers */ +} + +const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); + return i2c_ctrlr; +} + +const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) +{ + const struct soc_amd_genoa_config *config = config_of_soc(); + + *num_buses = ARRAY_SIZE(config->i2c); + return config->i2c; +} diff --git a/src/soc/amd/genoa/include/soc/i2c.h b/src/soc/amd/genoa/include/soc/i2c.h new file mode 100644 index 0000000..ffff754 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/i2c.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_I2C_H +#define AMD_GENOA_I2C_H + +#include <gpio.h> +#include <types.h> + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C4_SCL BIT(4) +#define GPIO_I2C5_SCL BIT(5) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL | \ + GPIO_I2C4_SCL | GPIO_I2C5_SCL) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_149 +#define I2C3_SCL_PIN GPIO_151 +#define I2C4_SCL_PIN GPIO_13 +#define I2C5_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_149_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_151_IOMUX_GPIOxx +#define I2C4_SCL_PIN_IOMUX_GPIOxx GPIO_13_IOMUX_GPIOxx +#define I2C5_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void reset_i2c_peripherals(void); + +#endif /* AMD_GENOA_I2C_H */ diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h index 5b767e3..0e24780 100644 --- a/src/soc/amd/genoa/include/soc/iomap.h +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -3,6 +3,10 @@ #ifndef AMD_GENOA_IOMAP_H #define AMD_GENOA_IOMAP_H +#define I2C_MASTER_DEV_COUNT 6 +#define I2C_PERIPHERAL_DEV_COUNT 0 +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + #define SPI_BASE_ADDRESS 0xfec10000 /* @Todo : Check these values for Genoa */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 Gerrit-Change-Number: 78900 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
by Nico Huber (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Elyes Haouas, Lennart Eichhorn, Patrick Georgi. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70771?usp=email ) Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 ...................................................................... Patch Set 29: (1 comment) File util/crossgcc/patches/gcc-11.4.0_ada-musl_workaround.patch: PS29: > While this patch seems obsolete, it still doesn't compile with musl. […] CB:79225 -- To view, visit https://review.coreboot.org/c/coreboot/+/70771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 29 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 22 Nov 2023 14:59:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: crossgcc: Fix build with musl libc
by Nico Huber (Code Review) 22 Nov '23

22 Nov '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79225?usp=email ) Change subject: crossgcc: Fix build with musl libc ...................................................................... crossgcc: Fix build with musl libc Work around an include-order issue when building against musl. When <sched.h> is included after GCC's "system.h", the build fails because calloc() is already poisoned by accident: sched.h:xx:y: error: attempt to use poisoned "calloc" Change-Id: I8ad28da70ec31aa8f7c6dad7a3371afbb614b86a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch 1 file changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/79225/1 diff --git a/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch new file mode 100644 index 0000000..552a7e7 --- /dev/null +++ b/util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch @@ -0,0 +1,122 @@ +Musl's <sched.h> uses calloc() which is marked as poisoned by GCC's +"system.h". Work around that by making sure that <sched.h> gets +included first. + +--- gcc-13.2.0/gcc/ada/adaint.c ++++ gcc-13.2.0.musl/gcc/ada/adaint.c +@@ -101,6 +101,10 @@ + #include <sys/time.h> + #endif + ++#if defined (__linux__) ++#include <sched.h> ++#endif ++ + #ifdef IN_RTS + + #ifdef STANDALONE +@@ -3441,7 +3445,6 @@ + #endif + + #if defined (__linux__) +-#include <sched.h> + + /* glibc versions earlier than 2.7 do not define the routines to handle + dynamically allocated CPU sets. For these targets, we use the static +--- gcc-13.2.0/gcc/ada/argv.c ++++ gcc-13.2.0.musl/gcc/ada/argv.c +@@ -42,6 +42,8 @@ + main program, and these routines are accessed from the + Ada.Command_Line.Environment package. */ + ++#include "adaint.h" ++ + #ifdef IN_RTS + #include "runtime.h" + #include <stdlib.h> +@@ -50,8 +52,6 @@ + #include "config.h" + #include "system.h" + #endif +- +-#include "adaint.h" + + #ifdef __cplusplus + extern "C" { +--- gcc-13.2.0/gcc/ada/cio.c ++++ gcc-13.2.0.musl/gcc/ada/cio.c +@@ -29,6 +29,8 @@ + * * + ****************************************************************************/ + ++#include "adaint.h" ++ + #ifdef IN_RTS + #include "runtime.h" + #include <sys/stat.h> +@@ -36,8 +38,6 @@ + #include "config.h" + #include "system.h" + #endif +- +-#include "adaint.h" + + /* We need L_tmpnam definition */ + #include <stdio.h> +--- gcc-13.2.0/gcc/ada/cstreams.c ++++ gcc-13.2.0.musl/gcc/ada/cstreams.c +@@ -58,14 +58,14 @@ + #include "vxWorks.h" + #endif + ++#include "adaint.h" ++ + #ifdef IN_RTS + #include <string.h> + #else + #include "config.h" + #include "system.h" + #endif +- +-#include "adaint.h" + + #ifdef __cplusplus + extern "C" { +--- gcc-13.2.0/gcc/ada/init.c ++++ gcc-13.2.0.musl/gcc/ada/init.c +@@ -53,6 +53,8 @@ + #undef __linux__ + #endif + ++#include "adaint.h" ++ + #ifdef IN_RTS + + #ifdef STANDALONE +@@ -71,7 +73,6 @@ + #include "system.h" + #endif + +-#include "adaint.h" + #include "raise.h" + + #ifdef __cplusplus +--- gcc-13.2.0/gcc/ada/raise.c ++++ gcc-13.2.0.musl/gcc/ada/raise.c +@@ -32,6 +32,8 @@ + /* Shared routines to support exception handling. __gnat_unhandled_terminate + is shared between all exception handling mechanisms. */ + ++#include "adaint.h" ++ + #ifdef IN_RTS + #include "runtime.h" + #else +@@ -39,7 +41,6 @@ + #include "system.h" + #endif + +-#include "adaint.h" + #include "raise.h" + + #ifdef __cplusplus -- To view, visit https://review.coreboot.org/c/coreboot/+/79225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ad28da70ec31aa8f7c6dad7a3371afbb614b86a Gerrit-Change-Number: 79225 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
by Nico Huber (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Elyes Haouas, Lennart Eichhorn, Patrick Georgi. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70771?usp=email ) Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 ...................................................................... Patch Set 29: (2 comments) File util/crossgcc/patches/gcc-11.4.0_ada-musl_workaround.patch: PS29: While this patch seems obsolete, it still doesn't compile with musl. I'm working on it... File util/crossgcc/patches/gcc-11.4.0_rv32iafc.patch: PS29: I can't find `iafc` in the 13.2 sources. Why was the patch removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/70771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 29 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 22 Nov 2023 14:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: src/arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
by Arthur Heymans (Code Review) 22 Nov '23

22 Nov '23

Attention is currently required from: Srinivas Hegde. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79218?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: src/arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: The '$$(call src-to-obj,$1,$$(1).ld):' target does the CPP so it can be omitted here. The commit message is not correct though. It's not erronously using CPPFLAGS, it's just superfluous. -- To view, visit https://review.coreboot.org/c/coreboot/+/79218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878 Gerrit-Change-Number: 79218 Gerrit-PatchSet: 2 Gerrit-Owner: Srinivas Hegde <srinivashegde(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Srinivas Hegde <srinivashegde(a)google.com> Gerrit-Comment-Date: Wed, 22 Nov 2023 13:48:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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