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Change subject: crossgcc: Fix build with musl libc
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Squashed into CB:70771.
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Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
......................................................................
Patch Set 30:
(1 comment)
File util/crossgcc/patches/gcc-11.4.0_ada-musl_workaround.patch:
PS29:
> CB:79225
Awesome! Thank you. May I include your sign-off in the commit message?
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Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
......................................................................
crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
Changelogs:
* https://gcc.gnu.org/gcc-12/changes.html
* https://gcc.gnu.org/gcc-13/changes.html
Porting guides:
* https://gcc.gnu.org/gcc-12/porting_to.html
* https://gcc.gnu.org/gcc-13/porting_to.html
Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
D util/crossgcc/patches/gcc-11.4.0_ada-musl_workaround.patch
D util/crossgcc/patches/gcc-11.4.0_gnat.patch
D util/crossgcc/patches/gcc-11.4.0_rv32iafc.patch
R util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch
A util/crossgcc/patches/gcc-13.2.0_gnat.patch
R util/crossgcc/patches/gcc-13.2.0_libcpp.patch
R util/crossgcc/patches/gcc-13.2.0_libgcc.patch
A util/crossgcc/patches/gcc-13.2.0_musl_poisoned_calloc.patch
D util/crossgcc/sum/gcc-11.4.0.tar.xz.cksum
A util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum
11 files changed, 238 insertions(+), 224 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/70771/30
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Change subject: Update vboot submodule to upstream main
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Hmmm... […]
edit: Can't add Ching-Kang directly here for some reason. Anyway, same problem was also reported on the Chromium CL now (CL:4798534).
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Change subject: mb/google/nissa: update GPP_F17 to edge trigger
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> interesting, we didn't find this in nivviks I think :)
The interrupt storm only happens with ITE ECs, not Nuvoton. I think changing it to edge triggered is correct regardless based on the spec linked from b/308539814#comment11: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/12_ACPI_Embedded_Controller_I… But there is still something unexplained about the ITE vs nuvoton behaviour.
Also I tested that wake still works on craask with this change.
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Change subject: Update vboot submodule to upstream main
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> With this patch we get problems when we build our mc_apl4 mainboard. […]
Hmmm... that would be a problem with your host environment, not the coreboot mainboard target you're building. Can you explain what operating system (e.g. Linux distribution and version) you're building on, what libc you're using and what version it is?
+Ching-Kang, any idea what could cause this? Do you know what libdl is and why Uwe needs to link it explicitly but we don't? Would anything break if we just added it? (I do see a `/usr/lib/libdl.a` in my CrOS chroot, but it seems to be an empty archive. I guess for some versions of glibc this is a separate library, but for others it is included in libc but the libdl file is still provided for compatibility? So should we just add `-ldl` to LDFLAGS unconditionally?)
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Change subject: vendorcode/amd: Hook up opensil
......................................................................
Patch Set 13:
(4 comments)
File src/vendorcode/amd/opensil/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/76511/comment/6372aa1b_c426286b :
PS13, Line 15: else
> it would make the code more readable to add a comment that this os the else branch for the if CONFIG […]
Done
https://review.coreboot.org/c/coreboot/+/76511/comment/9113c640_e4d8a9c7 :
PS13, Line 24: ifeq ($(CONFIG_OPENSIL_DEBUG_OUTPUT),y)
> add an empty line before this one, to have this if block that's unrelated to the ones before it sepa […]
Done
https://review.coreboot.org/c/coreboot/+/76511/comment/e19b39ad_a3d3c100 :
PS13, Line 30: ifeq ($(shell printf %.1s "$(obj)"),/)
> still need to figure out what this is doing exactly. […]
Done
https://review.coreboot.org/c/coreboot/+/76511/comment/34de70ab_00082f2a :
PS13, Line 46: $(CONFIG_C_ENV_BOOTBLOCK_SIZE)
> this should either be $(bios_size) or the bios_size definition in line 41 should be dropped
used $(bios_size) here
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Change subject: vendorcode/amd/opensil/genoa: Implement console callback
......................................................................
vendorcode/amd/opensil/genoa: Implement console callback
OpenSIL has an API to call back into the host firmware to print to the
console.
These could be moved to a common directory when there are more openSIL
implementations to see if it is actually common.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d
---
M src/vendorcode/amd/opensil/Makefile.inc
A src/vendorcode/amd/opensil/genoa_poc/Makefile.inc
A src/vendorcode/amd/opensil/genoa_poc/filter.h
M src/vendorcode/amd/opensil/genoa_poc/meson_cross.template
A src/vendorcode/amd/opensil/genoa_poc/opensil_console.c
A src/vendorcode/amd/opensil/genoa_poc/opensil_console.h
6 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/76512/9
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Felix Held has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76511?usp=email )
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Change subject: vendorcode/amd: Hook up opensil
......................................................................
vendorcode/amd: Hook up opensil
OpenSIL has a native buildsystem using meson and configuration mechanism
using kconfiglib.
To be able to use the coreboot toolchain with opensil, meson crossfiles
are used, which get generated by coreboot makefiles.
Configuration of opensil is done in a similar fashion with a template
defconfig after which kconfiglib is called to generate headers.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
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---
M src/vendorcode/amd/Kconfig
M src/vendorcode/amd/Makefile.inc
A src/vendorcode/amd/opensil/Kconfig
A src/vendorcode/amd/opensil/Kconfig.debug
A src/vendorcode/amd/opensil/Makefile.inc
A src/vendorcode/amd/opensil/genoa_poc/meson_cross.template
A src/vendorcode/amd/opensil/genoa_poc/opensil_config.template
7 files changed, 228 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/76511/14
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