coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[S] Change in coreboot[main]: soc/amd/mendocino: Add DBG2 table
by Bao Zheng (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd/mendocino: Add DBG2 table ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79174/comment/38446473_058f0105 : PS2, Line 9: 240426142 > 303689867 Done File src/soc/amd/mendocino/agesa_acpi.c: https://review.coreboot.org/c/coreboot/+/79174/comment/d7b71bfd_772b9ac6 : PS2, Line 30: Add table > DBG2? Done https://review.coreboot.org/c/coreboot/+/79174/comment/780ba198_85bddfaf : PS2, Line 31: 0xfedc9000 > I would probably use the configured console: […] Done. There is not field for baudrate in DBG2. https://review.coreboot.org/c/coreboot/+/79174/comment/7e156622_a6924470 : PS2, Line 31: current = acpi_16550_write_dbg2_uart(rsdp, current, 0xfedc9000, NULL); > shouldn't this call be put into an if CONFIG(AMD_SOC_CONSOLE_UART) block? i agree with Raul that the […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Nov 2023 07:03:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/mendocino: Add DBG2 table
by Bao Zheng (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, Zheng Bao. Hello Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Tim Wawrzynczak, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79174?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/mendocino: Add DBG2 table ...................................................................... soc/amd/mendocino: Add DBG2 table Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 CORE 20220331) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of dbg2.dat, Thu Nov 23 12:30:05 2023 * * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName:FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 0C [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 0000: 44 42 47 32 54 00 00 00 00 0C 43 4F 52 45 76 34 // DBG2T.....COREv4 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 0020: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 0030: 02 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&............. 0040: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 0050: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/mendocino/agesa_acpi.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/79174/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource
by Paul Menzel (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Benjamin Doron. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79228?usp=email ) Change subject: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79228/comment/858c37e5_2eda51a1 : PS1, Line 11: Is there any difference in the log messages? -- To view, visit https://review.coreboot.org/c/coreboot/+/79228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I106c1730787a88c03719acfb8a80e7b840b29997 Gerrit-Change-Number: 79228 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Nov 2023 06:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/intel/mtlrvp: define a new config for Chrome EC.
by Paul Menzel (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Kapil Porwal, Krishna P Bhat D, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79211?usp=email ) Change subject: mb/intel/mtlrvp: define a new config for Chrome EC. ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79211/comment/5605229d_9ea74ef5 : PS3, Line 7: mb/intel/mtlrvp: define a new config for Chrome EC. Please remove the dot/period at the end of the commit message summary. -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 3 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Thu, 23 Nov 2023 06:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Add DBG2 table
by Bao Zheng (Code Review) 23 Nov '23

23 Nov '23

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79248?usp=email ) Change subject: soc/amd/mendocino: Add DBG2 table ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/79248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79248 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Add DBG2 table
by Bao Zheng (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/79248?usp=email to review the following change. Change subject: soc/amd/mendocino: Add DBG2 table ...................................................................... soc/amd/mendocino: Add DBG2 table Dump the table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 CORE 20220331) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of dbg2.dat, Thu Nov 23 12:30:05 2023 * * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName:FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 0C [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 0000: 44 42 47 32 54 00 00 00 00 0C 43 4F 52 45 76 34 // DBG2T.....COREv4 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 0020: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 0030: 02 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&............. 0040: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 0050: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/mendocino/agesa_acpi.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/79248/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 17cd24c..b428bc3 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -896,6 +896,14 @@ name); } +unsigned long acpi_16550_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, + uint64_t base, const char *name) +{ + return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base, + 0x100, ACPI_ACCESS_SIZE_DWORD_ACCESS, + name); +} + static void acpi_create_facs(void *header) { acpi_facs_t *facs = header; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fe7e5fd..5bba9e8 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1631,6 +1631,8 @@ const struct device *dev, uint8_t access_size); unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, uint64_t base, const char *name); +unsigned long acpi_16550_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, + uint64_t base, const char *name); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); diff --git a/src/soc/amd/mendocino/agesa_acpi.c b/src/soc/amd/mendocino/agesa_acpi.c index d60a79d..e2d5668 100644 --- a/src/soc/amd/mendocino/agesa_acpi.c +++ b/src/soc/amd/mendocino/agesa_acpi.c @@ -8,6 +8,7 @@ #include <FspGuids.h> #include <soc/acpi.h> #include <types.h> +#include <console/uart.h> uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) @@ -27,5 +28,11 @@ current += ivrs->header.length; acpi_add_table(rsdp, ivrs); +#if CONFIG(AMD_SOC_CONSOLE_UART) + /* Add DBG2 table */ + current = acpi_16550_write_dbg2_uart(rsdp, current, + uart_platform_base(get_uart_for_console()), NULL); +#endif + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/79248?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79248 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: quandiso: p-sensor test
by Robert Chen (Code Review) 23 Nov '23

23 Nov '23

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79247?usp=email ) Change subject: quandiso: p-sensor test ...................................................................... quandiso: p-sensor test Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/quandiso/overridetree.cb 1 file changed, 30 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/79247/1 diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 64cd862..46da6d3 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -288,29 +288,29 @@ device ref i2c2 on chip drivers/i2c/sx9324 register "desc" = ""SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_gnrl_ctrl0" = "0x16" - register "reg_gnrl_ctrl1" = "0x21" - register "reg_afe_ctrl0" = "0x00" - register "reg_afe_ctrl1" = "0x10" - register "reg_afe_ctrl2" = "0x00" - register "reg_afe_ctrl3" = "0x00" - register "reg_afe_ctrl4" = "0x07" - register "reg_afe_ctrl5" = "0x00" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x0a" + register "reg_gnrl_ctrl1" = "0x22" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x47" register "reg_afe_ctrl6" = "0x00" - register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl7" = "0x47" register "reg_afe_ctrl8" = "0x12" register "reg_afe_ctrl9" = "0x0f" - register "reg_prox_ctrl0" = "0x12" - register "reg_prox_ctrl1" = "0x12" - register "reg_prox_ctrl2" = "0x90" - register "reg_prox_ctrl3" = "0x60" + register "reg_afe_ph0" = "0x37" + register "reg_afe_ph1" = "0x29" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" register "reg_prox_ctrl4" = "0x0c" - register "reg_prox_ctrl5" = "0x12" - register "reg_prox_ctrl6" = "0x3c" - register "reg_prox_ctrl7" = "0x58" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x2d" + register "reg_prox_ctrl7" = "0xc0" register "reg_adv_ctrl0" = "0x00" register "reg_adv_ctrl1" = "0x00" register "reg_adv_ctrl2" = "0x00" @@ -321,17 +321,20 @@ register "reg_adv_ctrl7" = "0x00" register "reg_adv_ctrl8" = "0x00" register "reg_adv_ctrl9" = "0x00" - register "reg_adv_ctrl10" = "0x5c" - register "reg_adv_ctrl11" = "0x52" - register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" register "reg_adv_ctrl13" = "0x00" register "reg_adv_ctrl14" = "0x80" register "reg_adv_ctrl15" = "0x0c" - register "reg_adv_ctrl16" = "0x38" - register "reg_adv_ctrl17" = "0x56" - register "reg_adv_ctrl18" = "0x33" - register "reg_adv_ctrl19" = "0xf0" - register "reg_adv_ctrl20" = "0xf0" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x40" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" device i2c 28 on probe DB_USB DB_1C_LTE end -- To view, visit https://review.coreboot.org/c/coreboot/+/79247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Gerrit-Change-Number: 79247 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts
by Eric Lai (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Felix Held, Leo Chou, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79184?usp=email ) Change subject: mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Gerrit-Change-Number: 79184 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Nov 2023 03:41:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts
by YH Lin (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Eric Lai, Felix Held, Leo Chou, Nick Vaccaro, Paul Menzel, Subrata Banik. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79184?usp=email ) Change subject: mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory parts ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Gerrit-Change-Number: 79184 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Nov 2023 02:43:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC
by Eric Lai (Code Review) 23 Nov '23

23 Nov '23

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Paul Menzel, Scott Chao. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79244?usp=email ) Change subject: mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS1: > The interrupt storm only happens with ITE ECs, not Nuvoton. […] oh I see. EC chip is different. Good to know. -- To view, visit https://review.coreboot.org/c/coreboot/+/79244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Gerrit-Change-Number: 79244 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 23 Nov 2023 02:10:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023