coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/amd/mendocino: Add DBG2 ACPI table
by Matt DeVillier (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Bao Zheng, Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Raul Rangel, Simon Glass, Tim Wawrzynczak, Zheng Bao. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79174?usp=email ) Change subject: soc/amd/mendocino: Add DBG2 ACPI table ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79174/comment/59ef32e7_58f01b18 : PS7, Line 7: mendocino needs updating File src/soc/amd/common/block/uart/uart.c: https://review.coreboot.org/c/coreboot/+/79174/comment/bac92231_80aa93f4 : PS7, Line 111: get_uart_for_console > Don't you want to check that the current device is equal to the selected console? The way this is wr […] it might make more sense to put this in `southbridge_write_acpi_tables()` in `src/soc/amd/common/block/acpi/tables.c` so it's only called once without having to check the index of each UART -- To view, visit https://review.coreboot.org/c/coreboot/+/79174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Gerrit-Change-Number: 79174 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Nov 2023 17:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: coreboot is awesome
by Felix Singer (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79300?usp=email ) Change subject: coreboot is awesome ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29a9fe845ce584d0acce6a426aa52b06958abce1 Gerrit-Change-Number: 79300 Gerrit-PatchSet: 1 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 17:09:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: coreboot is awesome
by Marvin Evers (Code Review) 28 Nov '23

28 Nov '23

Marvin Evers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79300?usp=email ) Change subject: coreboot is awesome ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29a9fe845ce584d0acce6a426aa52b06958abce1 Gerrit-Change-Number: 79300 Gerrit-PatchSet: 1 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 17:08:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Singer, Julius Werner, Lean Sheng Tan, Martin L Roth, Nico Huber, ron minnich. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 9: (3 comments) File src/arch/arm64/Kconfig: https://review.coreboot.org/c/coreboot/+/74798/comment/6c8af8a9_0ed23f4a : PS6, Line 30: 1 (EL1), 2 (EL2) and 3 (EL3) > These are standard Arm architectural terms (like "CPL0" on x86), I don't think we need to add more e […] Done https://review.coreboot.org/c/coreboot/+/74798/comment/7ca08d1b_81303cc7 : PS6, Line 41: depends on ARCH_RAMSTAGE_ARM64 > May want to add a `depends on ARM64_CURRENT_EL == 3` here, since this wouldn't work for other levels […] Done File src/arch/arm64/armv8/cpu.S: https://review.coreboot.org/c/coreboot/+/74798/comment/2611b168_8cc4fc94 : PS6, Line 87: #endif > Doing this everywhere looks pretty ugly. Can we add a macro like […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 9 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 16:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Milosevic, Felix Singer, Julius Werner, Lean Sheng Tan, Martin L Roth, Nico Huber, ron minnich. Hello Arthur Heymans, Christian Walter, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74798?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by ron minnich, Code-Review-1 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which lets us specify coreboot's EL upon entry. Based on that, we access the appropriate ELx registers. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/Kconfig M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/boot.c M src/arch/arm64/include/arch/asm.h M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 12 files changed, 117 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 10 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM config
by Matt DeVillier (Code Review) 28 Nov '23

28 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79306?usp=email ) Change subject: soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM config ...................................................................... soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM config Select PSP_VERSTAGE_MAP_ENTIRE_SPIROM in Cezanne Kconfig instead of common Kconfig. BUG=None TEST=Build BIOS image and boot to OS in dewatt. Change-Id: I476971700824fed06d17000001afc075105fa1ee Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79306 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/Kconfig 2 files changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 452e3ec..3700f18 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -22,6 +22,7 @@ select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK + select PSP_VERSTAGE_MAP_ENTIRE_SPIROM if VBOOT_STARTS_BEFORE_BOOTBLOCK select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 118ef61..f670291 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -46,7 +46,6 @@ config PSP_VERSTAGE_MAP_ENTIRE_SPIROM bool - default y if SOC_AMD_CEZANNE default n help This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. -- To view, visit https://review.coreboot.org/c/coreboot/+/79306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I476971700824fed06d17000001afc075105fa1ee Gerrit-Change-Number: 79306 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
by Matt DeVillier (Code Review) 28 Nov '23

28 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79155?usp=email ) Change subject: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable ...................................................................... soc/amd/common/psp_verstage: Make SPI ROM mapping configurable Earlier entire SPI ROM was mapped to memory. With limited TLB resources in PSP, this approach hit the limit on systems using 32 MiB SPI ROM. Therefore regions in SPI ROM were mapped on need basis. This works well on Picasso, Mendocino and Phoenix SoCs. But unfortunately this causes boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM and enable it in Cezanne SoC. For other SoCs, keep the configuration disabled so that only the required SPI ROM region is mapped. BUG=b:309690716 TEST=Build and boot to OS in both Dewatt and Skyrim. Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/boot_dev.c M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/psp_verstage.c 4 files changed, 30 insertions(+), 0 deletions(-) Approvals: Tim Van Patten: Looks good to me, but someone else must approve build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index dc6ea1c..118ef61 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -43,3 +43,11 @@ help This configuration indicates whether the PSP Verstage stack is mapped to a virtual address space. This has been the case so far only in Picasso SoC. + +config PSP_VERSTAGE_MAP_ENTIRE_SPIROM + bool + default y if SOC_AMD_CEZANNE + default n + help + This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. + This is required only in Cezanne SoC at the moment. diff --git a/src/soc/amd/common/psp_verstage/boot_dev.c b/src/soc/amd/common/psp_verstage/boot_dev.c index c129479..6ff1e2b 100644 --- a/src/soc/amd/common/psp_verstage/boot_dev.c +++ b/src/soc/amd/common/psp_verstage/boot_dev.c @@ -20,6 +20,8 @@ uint32_t ret; mdev = container_of(rd, __typeof__(*mdev), rdev); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return &(mdev->base[offset]); if (mdev->base) { if ((ret = svc_map_spi_rom(&mdev->base[offset], size, (void **)&mapping)) @@ -37,6 +39,9 @@ { uint32_t ret; + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return 0; + active_map_count--; if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) printk(BIOS_ERR, "Failed(%d) to unmap SPI ROM mapping %p\n", ret, mapping); diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index 0517545..5e46e68 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -97,6 +97,13 @@ if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM) && spi.SpiBiosSmnBase != 0) { + uintptr_t *addr = NULL; + + if (svc_map_spi_rom(spi.SpiBiosSmnBase, CONFIG_ROM_SIZE, (void **)&addr)) + printk(BIOS_DEBUG, "Error mapping SPI ROM to address.\n"); + return addr; + } return spi.SpiBiosSmnBase; } diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 87d126f2..7d9ef35 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -235,6 +235,7 @@ uint32_t retval; struct vb2_context *ctx = NULL; uint32_t bootmode; + void *boot_dev_base; /* * Do not use printk() before console_init() @@ -350,7 +351,16 @@ if (retval) reboot_into_recovery(ctx, retval); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) { + post_code(POSTCODE_UNMAP_SPI_ROM); + boot_dev_base = rdev_mmap_full(boot_device_ro()); + if (boot_dev_base) { + if (svc_unmap_spi_rom((void *)boot_dev_base)) + printk(BIOS_ERR, "Error unmapping SPI rom\n"); + } + } assert(!boot_dev_get_active_map_count()); + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); -- To view, visit https://review.coreboot.org/c/coreboot/+/79155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Gerrit-Change-Number: 79155 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Ivy Jian, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79102/comment/e1581dc0_9615ae10 : PS3, Line 1: Parent: 688da283 (mb/google/brox: Use Ti50 config) > GPP_E2 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 16:37:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Shelley Chen. Hello Eric Lai, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79102?usp=email to look at the new patch set (#4). Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... mb/google/brox: Fix configuration for TPM in Kconfig On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79102/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"
by Tim Van Patten (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Bao Zheng, Felix Held, Jason Nien, Martin Roth, Zheng Bao. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79172?usp=email ) Change subject: Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN" ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/variants/nipperkin/variant.c: PS3: Since this file is now empty, I think we can just delete it entirely and fall back to the base (`__weak`) version in `src/mainboard/google/guybrush/port_descriptors.c`. -- To view, visit https://review.coreboot.org/c/coreboot/+/79172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7 Gerrit-Change-Number: 79172 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Nov 2023 16:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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