coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[L] Change in coreboot[main]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Mike Banon. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64873?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches Conveniently and securely gets, checks SHA256 and installs some of my patches from this page - https://review.coreboot.org/q/status:open+banon - and also gets a collection of useful floppy-based operating systems. Sometimes it takes quite a long time to get a patch merged, while the people might need it today! - and this script could be really helpful. It asks a [Y/N] question for every addition, and since there are some "universal" patches as well as great floppies, you may still want to run this script - even if your board is not Lenovo G505S or not AMD. Use restore_agesa.sh script to restore AMD AGESA boards before running. Please share your feedback/suggestions and tell about other useful patches, preferably the "universal" ones - i.e. SeaBIOS. Currently included: 1) "board-specific": Lenovo G505S discrete GPU support, custom SeaBIOS options, example configs for G505S / AM1I-A / A88XM-E and known good AtomBIOS ROMs, and also good IRQ routing for AMD Lenovo G505S, ASUS A88XM-E and AM1I-A boards. 2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies, smbios_mptable_768; and also a floppies collection: KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird. Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ] Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2 --- A csb_patcher.sh 1 file changed, 926 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/64873/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/64873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2 Gerrit-Change-Number: 64873 Gerrit-PatchSet: 8 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Mike Banon. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64831?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: configs: add ASUS AM1I-A sample configuration ...................................................................... configs: add ASUS AM1I-A sample configuration This sample .config can be used ONLY if your git clone'd (and also git reset --hard to the revision mentioned at restore_agesa.sh script) coreboot source code has been processed with the following scripts: restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/76832 csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873 After you have executed the scripts above, you can use this .config as the base config for your AM1I-A by saving it to ./coreboot/.config - however, you may want to change some of its' configs! I.e. if you are using a SSD, you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". Also, I have disabled the Intel WiFi at this .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ] Change-Id: I639f7551cd59255a779f2ec03493a01bdc82cce8 --- A configs/config.asus_am1i-a 1 file changed, 703 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/64831/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/64831?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I639f7551cd59255a779f2ec03493a01bdc82cce8 Gerrit-Change-Number: 64831 Gerrit-PatchSet: 5 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Maximilian Brune, Naresh Solanki. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79086?usp=email ) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... Patch Set 4: (15 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79086/comment/bf864d34_e93bc55f : PS3, Line 7: sbsa > Would be good to explain what the SBSA acronym means (Server Base System Architecture) somewhere. Done File Documentation/mainboard/emulation/qemu-sbsa.md: https://review.coreboot.org/c/coreboot/+/79086/comment/9be93d17_09a3f1a1 : PS1, Line 6: <TF-A> > Can building TF-A be added to the makefile? It can be a in a follow-up. I would prefer doing that in a follow up. https://review.coreboot.org/c/coreboot/+/79086/comment/ac1c6b66_ce17c730 : PS1, Line 6: qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> \ : -pflash ./build/coreboot.rom \ > Add a 'qemu' make target so that it is as simple as running 'make qemu'. […] I would prefer doing that in a follow up. File src/mainboard/emulation/qemu-sbsa/Kconfig: https://review.coreboot.org/c/coreboot/+/79086/comment/59473875_279b4aa7 : PS3, Line 41: default y > Why? Done File src/mainboard/emulation/qemu-sbsa/Kconfig.name: https://review.coreboot.org/c/coreboot/+/79086/comment/7e49734a_488f28e6 : PS3, Line 4: o execute, do: : qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> -pflash ./build/coreboot.rom > These instructions would be better placed in documentation Done File src/mainboard/emulation/qemu-sbsa/Makefile.inc: https://review.coreboot.org/c/coreboot/+/79086/comment/f53f2f14_e73e252e : PS3, Line 23: truncate -s 256M $(obj)/coreboot.rom > Why is this needed? qemu-sbsa requires this, otherwise qemu does not start. File src/mainboard/emulation/qemu-sbsa/acpi.c: https://review.coreboot.org/c/coreboot/+/79086/comment/a6e26f0a_10fa45b6 : PS3, Line 36: his > Typo: his ---> This Done File src/mainboard/emulation/qemu-sbsa/board_info.txt: https://review.coreboot.org/c/coreboot/+/79086/comment/ba28d20b_488d5d56 : PS3, Line 3: http > HTTPS, please. […] Done File src/mainboard/emulation/qemu-sbsa/flash.fmd: https://review.coreboot.org/c/coreboot/+/79086/comment/68690061_685c3b29 : PS1, Line 17: @0x0 CONFIG_ROM_SIZE > not needed to specify Done https://review.coreboot.org/c/coreboot/+/79086/comment/5a033ee4_d54c45f6 : PS1, Line 20: @0x20000 > can also be dropped. Done File src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h: https://review.coreboot.org/c/coreboot/+/79086/comment/7e615446_8221ebf1 : PS3, Line 4: * Base addreses for QEMU sbsa-ref machine > > `'addreses' may be misspelled - perhaps 'addresses'?` […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/d7f7421b_eca97250 : PS3, Line 32: #define SBSA_PCIE_MMIO_HIGH_SIZE 0xff00000000 > Maybe align the values with tabs? Done File src/mainboard/emulation/qemu-sbsa/mainboard.c: https://review.coreboot.org/c/coreboot/+/79086/comment/d9fc4da1_a5dbd0b4 : PS3, Line 19: return (size_t)cbmem_top() - (uintptr_t)_dram;; > > `Statements terminations use 1 semicolon` […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/1484947c_06607ddd : PS3, Line 161: struct device *cpu = alloc_dev(dev->link_list, &devpath); > > `code indent should use tabs where possible` […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/b93842c5_a60a88d8 : PS3, Line 168: > nit: drop empty line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Gerrit-Change-Number: 79086 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 19:11:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Christian Walter, David Milosevic, Lean Sheng Tan, Maximilian Brune, Naresh Solanki. Hello Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Maximilian Brune, Naresh Solanki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79086?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... mainboard/emulation/qemu-sbsa: Add qemu-sbsa board Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). The Documentation is still a work-in-progress. Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A Documentation/mainboard/emulation/qemu-sbsa.md A src/mainboard/emulation/qemu-sbsa/Kconfig A src/mainboard/emulation/qemu-sbsa/Kconfig.name A src/mainboard/emulation/qemu-sbsa/Makefile.inc A src/mainboard/emulation/qemu-sbsa/acpi.c A src/mainboard/emulation/qemu-sbsa/board_info.txt A src/mainboard/emulation/qemu-sbsa/bootblock.c A src/mainboard/emulation/qemu-sbsa/bootblock_custom.S A src/mainboard/emulation/qemu-sbsa/cbmem.c A src/mainboard/emulation/qemu-sbsa/chip.h A src/mainboard/emulation/qemu-sbsa/devicetree.cb A src/mainboard/emulation/qemu-sbsa/dsdt.asl A src/mainboard/emulation/qemu-sbsa/flash.fmd A src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h A src/mainboard/emulation/qemu-sbsa/mainboard.c A src/mainboard/emulation/qemu-sbsa/media.c A src/mainboard/emulation/qemu-sbsa/memlayout.ld A src/mainboard/emulation/qemu-sbsa/mmio.c 18 files changed, 1,031 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79086/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Gerrit-Change-Number: 79086 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: configs: add ASUS A88XM-E sample configuration
by Mike Banon (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Mike Banon, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64832?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: configs: add ASUS A88XM-E sample configuration ...................................................................... configs: add ASUS A88XM-E sample configuration This sample .config can be used ONLY if your git clone'd (and also git reset --hard to the revision mentioned at restore_agesa.sh script) coreboot source code has been processed with the following scripts: restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/76832 csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873 After you have executed the scripts above, you can use this .config as the base config for your A88XM-E by saving it to ./coreboot/.config - however, you may want to change some of its' configs! I.e. if you are using a SSD, you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". Also, I have disabled the Intel WiFi at this .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ] Change-Id: I1e6387f97f2695270f1f73b2291572fa824c3c4b --- A configs/config.asus_a88xm-e 1 file changed, 701 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/64832/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/64832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e6387f97f2695270f1f73b2291572fa824c3c4b Gerrit-Change-Number: 64832 Gerrit-PatchSet: 5 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Julius Werner. David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79328?usp=email ) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... mainboard/emulation/qemu-sbsa: Add qemu-sbsa board Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). Change-Id: I19fbaeed991fc6dbc6c001765a9b9571bf9297a4 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A Documentation/mainboard/emulation/qemu-sbsa.md M src/arch/arm64/monitor_services.c A src/mainboard/emulation/qemu-sbsa/Kconfig A src/mainboard/emulation/qemu-sbsa/Kconfig.name A src/mainboard/emulation/qemu-sbsa/Makefile.inc A src/mainboard/emulation/qemu-sbsa/acpi.c A src/mainboard/emulation/qemu-sbsa/board_info.txt A src/mainboard/emulation/qemu-sbsa/bootblock.c A src/mainboard/emulation/qemu-sbsa/bootblock_custom.S A src/mainboard/emulation/qemu-sbsa/cbmem.c A src/mainboard/emulation/qemu-sbsa/chip.h A src/mainboard/emulation/qemu-sbsa/devicetree.cb A src/mainboard/emulation/qemu-sbsa/dsdt.asl A src/mainboard/emulation/qemu-sbsa/flash.fmd A src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h A src/mainboard/emulation/qemu-sbsa/mainboard.c A src/mainboard/emulation/qemu-sbsa/media.c A src/mainboard/emulation/qemu-sbsa/memlayout.ld A src/mainboard/emulation/qemu-sbsa/mmio.c 19 files changed, 1,032 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/79328/1 diff --git a/Documentation/mainboard/emulation/qemu-sbsa.md b/Documentation/mainboard/emulation/qemu-sbsa.md new file mode 100644 index 0000000..ccaf58d --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-sbsa.md @@ -0,0 +1,8 @@ +# QEMU SBSA emulator +This page describes how to build and run coreboot for QEMU's sbsa-ref machine. + +## Running coreboot in QEMU +```bash +qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> \ + -pflash ./build/coreboot.rom \ +``` diff --git a/src/arch/arm64/monitor_services.c b/src/arch/arm64/monitor_services.c index 38b9db0..b3ebb32 100644 --- a/src/arch/arm64/monitor_services.c +++ b/src/arch/arm64/monitor_services.c @@ -15,7 +15,7 @@ memset(&ret_args, 0, sizeof(ret_args)); - if (current_el() == EL3) { + if (CONFIG(ARM64_CURRENT_EL) == EL3) { printk(BIOS_DEBUG, "coreboot executes in EL3, assuming no monitor present...\n"); return ret_args; } diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig b/src/mainboard/emulation/qemu-sbsa/Kconfig new file mode 100644 index 0000000..6e1c2f8 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_EMULATION_QEMU_SBSA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_32768 + select BOOTBLOCK_CUSTOM + select BOOT_DEVICE_NOT_SPI_FLASH + select DRIVERS_UART_PL011 + select FLATTENED_DEVICE_TREE + select HAVE_LINEAR_FRAMEBUFFER + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MISSING_BOARD_RESET + select PCI + select HAVE_ACPI_TABLES + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select GENERATE_SMBIOS_TABLES + +config ARM64_CURRENT_EL + default 2 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xf0000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-sbsa/memlayout.ld" + +config FMDFILE + default "src/mainboard/emulation/qemu-sbsa/flash.fmd" + +config MAINBOARD_DIR + default "emulation/qemu-sbsa" + +config MAINBOARD_PART_NUMBER + default "QEMU sbsa" + +config MAX_CPUS + int + default 128 + +config MAINBOARD_VENDOR + string + default "QEMU" + +config DRAM_SIZE_MB + int + default 8388608 # The maximum dram size is 8192GiB. + +endif # BOARD_EMULATION_QEMU_SBSA diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig.name b/src/mainboard/emulation/qemu-sbsa/Kconfig.name new file mode 100644 index 0000000..3e52bcf --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_SBSA + bool "QEMU sbsa" diff --git a/src/mainboard/emulation/qemu-sbsa/Makefile.inc b/src/mainboard/emulation/qemu-sbsa/Makefile.inc new file mode 100644 index 0000000..e3855ba --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Makefile.inc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +ramstage-y += acpi.c + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -mcmodel=large -I$(src)/mainboard/$(MAINBOARDDIR)/include + +build_complete:: + @printf "Truncating coreboot.rom to 256M\n" + truncate -s 256M $(obj)/coreboot.rom diff --git a/src/mainboard/emulation/qemu-sbsa/acpi.c b/src/mainboard/emulation/qemu-sbsa/acpi.c new file mode 100644 index 0000000..1dae242 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/acpi.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> + + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->ARM_boot_arch |= ACPI_FADT_ARM_PSCI_COMPLIANT; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +uintptr_t platform_get_gicd_base(void) +{ + return SBSA_GIC_DIST; +} + +uintptr_t platform_get_gicr_base(void) +{ + return SBSA_GIC_REDIST; +} + +#define SEC_EL1_TIMER_GISV 0x1d +#define NONSEC_EL1_TIMER_GSIV 0x1e +#define VIRTUAL_TIMER_GSIV 0x1b +#define NONSEC_EL2_TIMER_GSIV 0x1a + +#define SBSA_TIMER_FLAGS (ACPI_GTDT_INTERRUPT_POLARITY | ACPI_GTDT_ALWAYS_ON) + +void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt) +{ + /* This value is optional if the system implements EL3 (Security + Extensions). If not provided, this field must be 0xFFFFFFFFFFFFFFFF. */ + gtdt->counter_block_address = UINT64_MAX; + gtdt->secure_el1_interrupt = SEC_EL1_TIMER_GISV; + gtdt->secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el1_interrupt = NONSEC_EL1_TIMER_GSIV; + gtdt->non_secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->virtual_timer_interrupt = VIRTUAL_TIMER_GSIV; + gtdt->virtual_timer_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el2_interrupt = NONSEC_EL2_TIMER_GSIV; + gtdt->non_secure_el2_flags = SBSA_TIMER_FLAGS; + /* This value is optional if the system implements EL3 + (Security Extensions). If not provided, this field must be + 0xFFFFFFFFFFFFFFF. */ + gtdt->counter_read_block_address = UINT64_MAX; +} + +#define WD_TIMER_GSIV 0x30 + +unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current) +{ + (*count)++; + return acpi_gtdt_add_watchdog(current, SBSA_GWDT_REFRESH, SBSA_GWDT_CONTROL, + WD_TIMER_GSIV, 0); +} diff --git a/src/mainboard/emulation/qemu-sbsa/board_info.txt b/src/mainboard/emulation/qemu-sbsa/board_info.txt new file mode 100644 index 0000000..16a92be --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU sbsa +Category: emulation +Board URL: https://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock.c b/src/mainboard/emulation/qemu-sbsa/bootblock.c new file mode 100644 index 0000000..473189e --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <symbols.h> + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* Everything below DRAM is device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW); + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) CONFIG_DRAM_SIZE_MB) * MiB, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW); + mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW); + mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S new file mode 100644 index 0000000..c05afed --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Early initialization code for sbsa-ref machine + */ + +#include <arch/asm.h> + +ENTRY(_start) + + /* TF-A arg which contains a pointer to fdt */ + ldr x1, =_fdt_pointer + str x0, [x1] + + /* Setup CPU. */ + /* bl arm64_init_cpu */ + + /* ==== stack init from arm64_init_cpu ==== */ + + msr SPSel, #0 /* use SP_EL0 */ + + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + sub sp, x0, #16 + + /* ==== END ==== */ + + /* Get code positions. */ + ldr x1, =_flash + ldr x0, =_bootblock + + /* Calculate bootblock size. */ + ldr x2, =_ebootblock + sub x2, x2, x0 + + /* Call memcpy in arch/arm64/memcpy.S */ + bl memcpy + dmb sy + + /* Calculate relocation offset between bootblock in flash and in DRAM. */ + ldr x0, =_flash + ldr x1, =_bootblock + sub x1, x1, x0 + + /* Jump to main() in DRAM. */ + adr x0, main + add x0, x0, x1 + blr x0 +ENDPROC(_start) diff --git a/src/mainboard/emulation/qemu-sbsa/cbmem.c b/src/mainboard/emulation/qemu-sbsa/cbmem.c new file mode 100644 index 0000000..389ff4e --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/cbmem.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cbmem.h> +#include <ramdetect.h> +#include <symbols.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/emulation/qemu-sbsa/chip.h b/src/mainboard/emulation/qemu-sbsa/chip.h new file mode 100644 index 0000000..98c6c71 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H +#define MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H + +#include <types.h> + +struct mainboard_emulation_qemu_sbsa_config { + uint32_t vgic_maintenance_interrupt; + uint32_t performance_interrupt_gsiv; +}; + +#endif diff --git a/src/mainboard/emulation/qemu-sbsa/devicetree.cb b/src/mainboard/emulation/qemu-sbsa/devicetree.cb new file mode 100644 index 0000000..2e2cf3d --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/devicetree.cb @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip mainboard/emulation/qemu-sbsa + register "vgic_maintenance_interrupt" = "0x19" + register "performance_interrupt_gsiv" = "0x17" + + device cpu_cluster 0 on ops qemu_aarch64_cpu_ops end + + device domain 0 on ops qemu_aarch64_pci_domain_ops + device pci 00.0 on end + end +end diff --git a/src/mainboard/emulation/qemu-sbsa/dsdt.asl b/src/mainboard/emulation/qemu-sbsa/dsdt.asl new file mode 100644 index 0000000..e7d4251 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/dsdt.asl @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LINK_DEVICE(Uid, LinkName, Irq) \ + Device (LinkName) { \ + Name (_HID, EISAID("PNP0C0F")) \ + Name (_UID, Uid) \ + Name (_PRS, ResourceTemplate() { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ + }) \ + Method (_STA) { \ + Return (0xF) \ + } \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, Pin, Link, Zero \ + } + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230621 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SBSA_UART_BASE, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + Method (_STA) { + Return (0xF) + } + } + + // AHCI Host Controller + Device (AHC0) { + Name (_HID, "LNRO001E") + Name (_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_AHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + Method (_STA) { + Return (0xF) + } + } + + // USB EHCI Host Controller + Device (USB0) { + Name (_HID, "LNRO0D20") + Name (_CID, "PNP0D20") + Method (_STA) { + Return (0xF) + } + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_EHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 } + }) + Return (RBUF) + } + + // Root Hub + Device (RHUB) { + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec + Method (_STA) { + Return (0xF) + } + + // Ports connected to Root Hub + Device (HUB1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + Method (_STA) { + Return (0xF) + } + + Device (PRT1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT1 + Device (PRT2) { + Name (_ADR, 0x00000002) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT2 + + Device (PRT3) { + Name (_ADR, 0x00000003) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT3 + + Device (PRT4) { + Name (_ADR, 0x00000004) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_STA) { + Return (0xF) + } + + Method (_CBA, 0, NotSerialized) { + return (SBSA_PCIE_ECAM_BASE) + } + + LINK_DEVICE(0, GSI0, 0x23) + LINK_DEVICE(1, GSI1, 0x24) + LINK_DEVICE(2, GSI2, 0x25) + LINK_DEVICE(3, GSI3, 0x26) + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 0, GSI1), + PRT_ENTRY(0x0000FFFF, 0, GSI2), + PRT_ENTRY(0x0000FFFF, 0, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_BASE, // Min Base Address + SBSA_PCIE_MMIO_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_HIGH_BASE, // Min Base Address + SBSA_PCIE_MMIO_HIGH_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_HIGH_SIZE // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0, // Min Base Address + 0xffff, // Max Base Address + SBSA_PCIE_PIO_BASE, // Translate + 0x10000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + SBSA_PCIE_ECAM_BASE, // Range Minimum + SBSA_PCIE_ECAM_LIMIT, // Range Maximum + 0x0000000000000000, // Translation Offset + SBSA_PCIE_ECAM_SIZE, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Method (_STA) { + Return (0xF) + } + } + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If ((SUPP & 0x16) != 0x16) { + CTRL &= 0x1E // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + CTRL &= 0x1D + + If (Arg1 != One) { // Unknown revision + CDW1 |= 0x08 + } + + If (CDW3 != CTRL) { // Capabilities bits were masked + CDW1 |= 0x10 + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } + } // Scope (_SB) +} diff --git a/src/mainboard/emulation/qemu-sbsa/flash.fmd b/src/mainboard/emulation/qemu-sbsa/flash.fmd new file mode 100644 index 0000000..fcc6e19 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/flash.fmd @@ -0,0 +1,23 @@ +# +# custom fmap which takes the additional TF-A region into account +# +# +-------------+ <-- 0x0 +# | TF-A | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE +# + +FLASH@0x10000000 CONFIG_ROM_SIZE { + + BIOS { + + BOOTBLOCK 128K + FMAP 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h new file mode 100644 index 0000000..dd3de70 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Base addresses for QEMU sbsa-ref machine + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ + +#define SBSA_FLASH_BASE 0x00000000 +#define SBSA_FLASH_SIZE 0x20000000 +#define SBSA_GIC_DIST 0x40060000 +#define SBSA_GIC_REDIST 0x40080000 +#define SBSA_GWDT_REFRESH 0x50010000 +#define SBSA_GWDT_CONTROL 0x50011000 +#define SBSA_UART_BASE 0x60000000 +#define SBSA_RTC_BASE 0x60010000 +#define SBSA_GPIO_BASE 0x60020000 +#define SBSA_SECURE_UART_BASE 0x60030000 +#define SBSA_SMMU_BASE 0x60050000 +#define SBSA_AHCI_BASE 0x60100000 +#define SBSA_EHCI_BASE 0x60110000 +#define SBSA_SECMEM_BASE 0x20000000 +#define SBSA_SECMEM_SIZE 0x20000000 +#define SBSA_PCIE_MMIO_BASE 0x80000000 +#define SBSA_PCIE_MMIO_LIMIT 0xefffffff +#define SBSA_PCIE_MMIO_SIZE 0x70000000 +#define SBSA_PCIE_PIO_BASE 0x7fff0000 +#define SBSA_PCIE_ECAM_BASE 0xf0000000 +#define SBSA_PCIE_ECAM_LIMIT 0xffffffff +#define SBSA_PCIE_ECAM_SIZE 0x10000000 +#define SBSA_PCIE_MMIO_HIGH_BASE 0x100000000 +#define SBSA_PCIE_MMIO_HIGH_LIMIT 0xffffffffff +#define SBSA_PCIE_MMIO_HIGH_SIZE 0xff00000000 diff --git a/src/mainboard/emulation/qemu-sbsa/mainboard.c b/src/mainboard/emulation/qemu-sbsa/mainboard.c new file mode 100644 index 0000000..755fdc9 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mainboard.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "chip.h" +#include <acpi/acpigen.h> +#include <arch/mmu.h> +#include <bootmem.h> +#include <cbfs.h> +#include <device/device.h> +#include <device_tree.h> +#include <bootmem.h> +#include <arch/mmu.h> +#include <mainboard/addressmap.h> +#include <ramdetect.h> +#include <stdint.h> +#include <symbols.h> + +static size_t ram_size(void) +{ + return (size_t)cbmem_top() - (uintptr_t)_dram; +} + +static void mainboard_init(void *chip_info) +{ + mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); +} + +DECLARE_REGION(fdt_pointer) +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) +{ + *core_count = 0; + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) + *core_count += 1; + + *thread_count = 1; +} + +static void qemu_aarch64_init(struct device *dev) +{ + struct memory_info *mem_info; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; + mem_info->max_capacity_mib = 0x800000; // Fixed at 8 TiB for qemu-sbsa + mem_info->number_of_devices = mem_info->dimm_cnt = 1; + + mem_info->dimm[0].dimm_size = ram_size() / MiB; + mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; + mem_info->dimm[0].ddr_frequency = 0; + mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; + mem_info->dimm[0].bank_locator = 0; + + mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity + mem_info->dimm[0].vdd_voltage = 0; + mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; +} + +static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "ACPI: * DBG2\n"); + return acpi_pl011_write_dbg2_uart(rsdp, current, SBSA_UART_BASE, "\\_SB.COM0"); +} + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = qemu_aarch64_init; + dev->ops->write_acpi_tables = mb_write_acpi_tables; +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; + +struct chip_operations mainboard_emulation_qemu_sbsa_ops = { }; + +static void qemu_aarch64_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, index++); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_BASE; + res->limit = SBSA_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_HIGH_BASE; + res->limit = SBSA_PCIE_MMIO_HIGH_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + mmio_range(dev, index++, SBSA_PCIE_ECAM_BASE, SBSA_PCIE_ECAM_SIZE); + + ram_range(dev, index++, (uintptr_t)_dram, ram_size()); + + mmio_range(dev, index++, SBSA_FLASH_BASE, SBSA_FLASH_SIZE); + reserved_ram_range(dev, index++, SBSA_SECMEM_BASE, SBSA_SECMEM_SIZE); +} + +struct device_operations qemu_aarch64_pci_domain_ops = { + .read_resources = qemu_aarch64_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +static void qemu_sbsa_fill_cpu_ssdt(const struct device *dev) +{ + acpigen_write_processor_device(dev->path.gicc_v3.mpidr); + acpigen_write_processor_device_end(); +} + +struct device_operations qemu_sbsa_cpu_ops = { + .acpi_fill_ssdt = qemu_sbsa_fill_cpu_ssdt, +}; + +static void qemu_aarch64_scan_bus(struct device *dev) +{ + if (!dev->link_list) + add_more_links(dev, 1); + + uintptr_t fdt_blob = *(uintptr_t *)_fdt_pointer; + struct device_tree *tree; + char path[14]; + u16 fdt_cpu_count = 0; + struct mainboard_emulation_qemu_sbsa_config *config = dev->chip_info; + + tree = fdt_unflatten((void *)fdt_blob); + if (tree == NULL) + return; + snprintf(path, sizeof(path), "/cpus/cpu@%d", fdt_cpu_count); + for (struct device_tree_node *node = dt_find_node_by_path(tree, path, NULL, NULL, 0); node;) { + struct device_tree_property *prop; + int64_t mpidr = -1; + list_for_each(prop, node->properties, list_node) { + if (!strcmp("reg", prop->prop.name)) { + mpidr = be64toh(*(uint64_t *)prop->prop.data); + break; + } + } + if (mpidr >= 0) { + struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, + .gicc_v3 = { .mpidr = mpidr, + .vgic_mi = config->vgic_maintenance_interrupt, + .pi_gsiv = config->performance_interrupt_gsiv, }, + + }; + struct device *cpu = alloc_dev(dev->link_list, &devpath); + assert(cpu); + cpu->ops = &qemu_sbsa_cpu_ops; + } + snprintf(path, sizeof(path), "/cpus/cpu@%d", ++fdt_cpu_count); + node = dt_find_node_by_path(tree, path, NULL, NULL, 0); + } +} + +struct device_operations qemu_aarch64_cpu_ops = { + .scan_bus = qemu_aarch64_scan_bus, +}; diff --git a/src/mainboard/emulation/qemu-sbsa/media.c b/src/mainboard/emulation/qemu-sbsa/media.c new file mode 100644 index 0000000..00ed54c --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/media.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)0x10000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-sbsa/memlayout.ld b/src/mainboard/emulation/qemu-sbsa/memlayout.ld new file mode 100644 index 0000000..885d766 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/memlayout.ld @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for QEMU sbsa-ref machine since + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ +SECTIONS +{ + REGION(flash, 0x10000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x10000000000) + BOOTBLOCK(0x10020010000, 64K) + STACK(0x10020020000, 54K) + CBFS_MCACHE(0x1002002D800, 8K) + FMAP_CACHE(0x1002002F800, 2K) + TIMESTAMP(0x10020030000, 1K) + ROMSTAGE(0x10020031000, 128K) + TTB(0x10020070000, 128K) + RAMSTAGE(0x100200b0000, 16M) + REGION(fdt_pointer, 0x100210b0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0x10021200000, 1M) +} diff --git a/src/mainboard/emulation/qemu-sbsa/mmio.c b/src/mainboard/emulation/qemu-sbsa/mmio.c new file mode 100644 index 0000000..6b50856 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mmio.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/uart.h> +#include <mainboard/addressmap.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + return SBSA_UART_BASE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79328?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19fbaeed991fc6dbc6c001765a9b9571bf9297a4 Gerrit-Change-Number: 79328 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: arch/arm64: Implement initial set of SMBIOS tables
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: David Milosevic, Julius Werner, Lean Sheng Tan, Martin L Roth, Maximilian Brune. David Milosevic has uploaded a new patch set (#9) to the change originally created by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/78285?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Implement initial set of SMBIOS tables ...................................................................... arch/arm64: Implement initial set of SMBIOS tables Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Need to confirm tables are in fact compliant. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/Kconfig M src/arch/arm64/Makefile.inc A src/arch/arm64/smbios.c M src/arch/arm64/tables.c M src/include/smbios.h 5 files changed, 233 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78285/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/78285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Gerrit-Change-Number: 78285 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: arch/arm64: Support calling a trusted monitor
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: David Milosevic, Julius Werner, Lean Sheng Tan. David Milosevic has uploaded a new patch set (#9) to the change originally created by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/78284?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Support calling a trusted monitor ...................................................................... arch/arm64: Support calling a trusted monitor Implement support for generating an SMC to call a trusted monitor. Some functions are provided to read the SoC ID from the monitor, if supported. Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/arch/arm64/Makefile.inc A src/arch/arm64/include/armv8/arch/monitor_services.h A src/arch/arm64/monitor_services.c 3 files changed, 165 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/78284/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/78284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Gerrit-Change-Number: 78284 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Milosevic, Felix Singer, Julius Werner, Lean Sheng Tan, Martin L Roth, Nico Huber, ron minnich. Hello Arthur Heymans, Christian Walter, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74798?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which lets us specify coreboot's EL upon entry. Based on that, we access the appropriate ELx registers. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/Kconfig M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/boot.c M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 11 files changed, 142 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 13 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: configs: add Lenovo G505S sample configuration (use with dGPU patches)
by Mike Banon (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Mike Banon. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64829?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches) ...................................................................... configs: add Lenovo G505S sample configuration (use with dGPU patches) This sample .config can be used ONLY if your git clone'd (and also git reset --hard to the revision mentioned at restore_agesa.sh script) coreboot source code has been processed with the following scripts: restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/76832 csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873 After you have executed the scripts above, you can use this .config as the base config for your G505S by saving it to ./coreboot/.config - however, you may want to change some of its' configs! I.e. it specifies CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" CONFIG_VGA_BIOS_DGPU_ID="1002,6665" which is compatible with R5-M230 dGPU, but if your G505S has HD-8570M discrete GPU instead - you will need to change these configs to ",6663". Or, if your G505S does not have a discrete GPU at all, please disable CONFIG_AMD_DGPU_WITHOUT_EEPROM=y and those DGPU configs will be disabled. Also, if you are using a SSD - may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". Also I've disabled the Intel WiFi at my .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ] Change-Id: I20557628d47ca120a52a8c73635e25d7c39789bf --- A configs/config.lenovo_g505s_use_with_dgpu_patches 1 file changed, 691 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/64829/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/64829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20557628d47ca120a52a8c73635e25d7c39789bf Gerrit-Change-Number: 64829 Gerrit-PatchSet: 5 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023