coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Eric Lai, Ivy Jian, Karthik Ramasubramanian, Nick Vaccaro. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79101?usp=email ) Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... Patch Set 5: (3 comments) File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79101/comment/c88caf24_9027de57 : PS1, Line 88: .i2c[0] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[1] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[2] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 900, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[3] = { : .early_init = 1, : .speed = I2C_SPEED_FAST, : .rise_time_ns = 600, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : .i2c[5] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 650, : .fall_time_ns = 400, : .data_hold_time_ns = 50, : }, : > Hey Nick, in the past we could set these with through tuning with the help of a hw engineer. […] Ok, I talked to Nick offline and he said to reorder the configs to match the order of the devices listed in the comments. File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79101/comment/d53fadea_6d38419e : PS4, Line 107: .early_init = 1, > Now that GSC is in I2C4, this should be for i2c[4]. Done https://review.coreboot.org/c/coreboot/+/79101/comment/83f84158_c43901bb : PS4, Line 169: device ref i2c3 on end > Can be removed, not that nothing is in I2C3. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 21:00:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Milosevic, Felix Singer, Julius Werner, Lean Sheng Tan, Martin L Roth, Nico Huber, ron minnich. Hello Arthur Heymans, Christian Walter, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74798?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which lets us specify coreboot's EL upon entry. Based on that, we access the appropriate ELx registers. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/Kconfig M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/boot.c M src/arch/arm64/include/arch/asm.h M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 12 files changed, 117 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 14 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Shelley Chen (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Eric Lai, Ivy Jian, Nick Vaccaro, Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79101?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... mb/google/brox: Set TPM i2c config in device tree Insert TPM device into i2c4 slot in the device tree. Also make sure the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I10a7463effd85aec4551385963197bc1021319fe Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 19 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79101/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79332?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 ...................................................................... mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID. TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79332/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Gerrit-Change-Number: 79332 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79332?usp=email ) Change subject: mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 ...................................................................... mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14 This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID. TEST=Able to perform power limit configuration for google/ovis. Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/79332/1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index 17d39ae..1eec1ec 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -19,6 +19,15 @@ .pl2_max_power = 64000, .pl4_power = 120000 }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_3, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, }; void __weak variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/79332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Gerrit-Change-Number: 79332 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Maximilian Brune, Naresh Solanki. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79086?usp=email ) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... Patch Set 5: (15 comments) File src/mainboard/emulation/qemu-sbsa/dsdt.asl: https://review.coreboot.org/c/coreboot/+/79086/comment/5e01df8a_e3f81f16 : PS1, Line 419: Device (RES0) : { : Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID : Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings : { : QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, : 0x0000000000000000, // Granularity : SBSA_PCIE_ECAM_BASE, // Range Minimum : SBSA_PCIE_ECAM_LIMIT, // Range Maximum : 0x0000000000000000, // Translation Offset : SBSA_PCIE_ECAM_SIZE, // Length : ,, , AddressRangeMemory, TypeStatic) : }) : Method (_STA) { : Return (0xF) : } : } > Drop this. It's in dsdt_top.asl now. Done File src/mainboard/emulation/qemu-sbsa/dsdt.asl: https://review.coreboot.org/c/coreboot/+/79086/comment/e8832792_ab1c3222 : PS3, Line 10: Method (_STA) { \ : Return (0xF) \ : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/ef157a5d_cb8e9e4a : PS3, Line 15: Method (_DIS) { } \ > If _DIS does nothing, should it even exist? Done https://review.coreboot.org/c/coreboot/+/79086/comment/6d2d0177_50902241 : PS3, Line 21: } > nit: closing brace is indented a bit too much Done https://review.coreboot.org/c/coreboot/+/79086/comment/06832e8d_0d5bf313 : PS3, Line 31: // OEM revision > Most instances of this comment are copy-pasta from other boards. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/a8f2799d_34982e7b : PS3, Line 45: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/c4dc3a35_1a2345f1 : PS3, Line 63: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/49cac825_47aedd3c : PS3, Line 70: Name (_HID, "LNRO0D20") > Indentation went up an extra level here and in the following blocks Done https://review.coreboot.org/c/coreboot/+/79086/comment/38a5f462_1f3f745a : PS3, Line 72: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/6ecaa002_00493f57 : PS3, Line 86: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/3848b792_21ef0b00 : PS3, Line 117: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/d631c4dc_99387424 : PS3, Line 190: Method (_STA) { : Return (0xF) : } > _STA that always returns 0xf can be removed: https://uefi. […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/438ff087_a79df4a6 : PS3, Line 205: PRT_ENTRY(0x0000FFFF, 0, GSI0), : PRT_ENTRY(0x0000FFFF, 0, GSI1), : PRT_ENTRY(0x0000FFFF, 0, GSI2), : PRT_ENTRY(0x0000FFFF, 0, GSI3), > Pin is always 0 for these 4 entries, is this correct? It seems odd. Done https://review.coreboot.org/c/coreboot/+/79086/comment/759be827_155649eb : PS3, Line 210: PRT_ENTRY(0x0001FFFF, 0, GSI1), : PRT_ENTRY(0x0001FFFF, 1, GSI2), : PRT_ENTRY(0x0001FFFF, 2, GSI3), : PRT_ENTRY(0x0001FFFF, 3, GSI0), > Idea: For the sake of brevity, you could define another helper function: […] Done https://review.coreboot.org/c/coreboot/+/79086/comment/67860bfb_cd254ba4 : PS3, Line 453: Store (CDW2,SUPP) : Store (CDW3,CTRL) > Should be equivalent: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Gerrit-Change-Number: 79086 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 20:20:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, David Milosevic, Lean Sheng Tan, Maximilian Brune, Naresh Solanki. Hello Arthur Heymans, Benjamin Doron, Christian Walter, Lean Sheng Tan, Maximilian Brune, Naresh Solanki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79086?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... mainboard/emulation/qemu-sbsa: Add qemu-sbsa board Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). The Documentation is still a work-in-progress. Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A Documentation/mainboard/emulation/qemu-sbsa.md A src/mainboard/emulation/qemu-sbsa/Kconfig A src/mainboard/emulation/qemu-sbsa/Kconfig.name A src/mainboard/emulation/qemu-sbsa/Makefile.inc A src/mainboard/emulation/qemu-sbsa/acpi.c A src/mainboard/emulation/qemu-sbsa/board_info.txt A src/mainboard/emulation/qemu-sbsa/bootblock.c A src/mainboard/emulation/qemu-sbsa/bootblock_custom.S A src/mainboard/emulation/qemu-sbsa/cbmem.c A src/mainboard/emulation/qemu-sbsa/chip.h A src/mainboard/emulation/qemu-sbsa/devicetree.cb A src/mainboard/emulation/qemu-sbsa/dsdt.asl A src/mainboard/emulation/qemu-sbsa/flash.fmd A src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h A src/mainboard/emulation/qemu-sbsa/mainboard.c A src/mainboard/emulation/qemu-sbsa/media.c A src/mainboard/emulation/qemu-sbsa/memlayout.ld A src/mainboard/emulation/qemu-sbsa/mmio.c 18 files changed, 858 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79086/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Gerrit-Change-Number: 79086 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/rex: Simplify power limit configuration usage
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79331?usp=email ) Change subject: mb/google/rex: Simplify power limit configuration usage ...................................................................... mb/google/rex: Simplify power limit configuration usage This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c 2 files changed, 1 insertion(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/79331/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 011c7a9..a7f7b06 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -239,17 +239,4 @@ config HAVE_SLP_S0_GATE def_bool n -choice - prompt "Choose desired processor power limits (PLs)" - default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO - default PL_PERFORMANCE - -config PL_PERFORMANCE - bool "Performance: Maximum PLs for maximum performance" - -config PL_BASELINE - bool "Baseline: Baseline PLs for balanced performance at lower power" - -endchoice - endif # BOARD_GOOGLE_REX_COMMON diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index 7c096510..14fbad2 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -10,7 +10,7 @@ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) * Following values are for performance config as per document #640982 */ -#if CONFIG(PL_PERFORMANCE) + const struct cpu_tdp_power_limits performance_efficient_limits[] = { { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, @@ -52,49 +52,6 @@ .pl4_power = 64000 }, }; -#else -const struct cpu_tdp_power_limits performance_efficient_limits[] = { - { - .mch_id = PCI_DID_INTEL_MTL_P_ID_2, - .cpu_tdp = 15, - .pl1_min_power = 10000, - .pl1_max_power = 15000, - .pl2_min_power = 40000, - .pl2_max_power = 40000, - .pl4_power = 84000 - }, - { - .mch_id = PCI_DID_INTEL_MTL_P_ID_5, - .cpu_tdp = 15, - .pl1_min_power = 10000, - .pl1_max_power = 15000, - .pl2_min_power = 40000, - .pl2_max_power = 40000, - .pl4_power = 84000 - }, -}; - -const struct cpu_tdp_power_limits power_optimized_limits[] = { - { - .mch_id = PCI_DID_INTEL_MTL_P_ID_2, - .cpu_tdp = 15, - .pl1_min_power = 10000, - .pl1_max_power = 15000, - .pl2_min_power = 40000, - .pl2_max_power = 40000, - .pl4_power = 47000 - }, - { - .mch_id = PCI_DID_INTEL_MTL_P_ID_5, - .cpu_tdp = 15, - .pl1_min_power = 10000, - .pl1_max_power = 15000, - .pl2_min_power = 40000, - .pl2_max_power = 40000, - .pl4_power = 47000 - }, -}; -#endif void __weak variant_devtree_update(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79331?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Gerrit-Change-Number: 79331 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/rex/var/screebo: Override power limits
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79330?usp=email ) Change subject: mb/google/rex/var/screebo: Override power limits ...................................................................... mb/google/rex/var/screebo: Override power limits This patch modifies the power limits value to enhance power management for the google/screebo variant. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 25000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/screebo/variant.c 1 file changed, 65 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/79330/1 diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c index 4ea6598..e9b31b6 100644 --- a/src/mainboard/google/rex/variants/screebo/variant.c +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <chip.h> -#include <fw_config.h> #include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) @@ -26,3 +27,65 @@ config->tcss_aux_ori = 0x04; } } + +const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits variant_power_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; + +void variant_devtree_update(void) +{ + const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits; + size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = variant_power_efficient_limits; + limits_size = ARRAY_SIZE(variant_power_efficient_limits); + } + } + + variant_update_cpu_power_limits(limits, limits_size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Gerrit-Change-Number: 79330 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/rex: Enhance power limit override mechanism
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79329?usp=email ) Change subject: mb/google/rex: Enhance power limit override mechanism ...................................................................... mb/google/rex: Enhance power limit override mechanism This patch expands the power limit override capability to include variants directories, enabling them to modify power limit settings configured by the baseboard. Previously, only the baseboard could override power limit settings. For instance, while the google/rex baseboard sets the PL1 max power limit to 15W, the google/screebo variant couldn't override this value. This enhancement empowers variants directories to override baseboard- configured power limit settings, allowing for greater flexibility and control over power limits. BUG=b:313667378 TEST=Able to call into _weak implementation of `variant_devtree_update` unless there is one override. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/79329/1 diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index 619ca71..3ca85ff 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -41,12 +41,12 @@ fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); - variant_devtree_update(); + baseboard_devtree_update(); } -void __weak variant_devtree_update(void) +void __weak baseboard_devtree_update(void) { - /* Override dev tree settings per board */ + /* Override dev tree settings per baseboard */ } void __weak variant_generate_s0ix_hook(enum s0ix_entry entry) diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index afed754..bd3d535 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -31,7 +31,9 @@ void variant_generate_s0ix_hook(enum s0ix_entry entry); -/* Modify devictree settings during ramstage */ +/* Modify devictree settings during ramstage by baseboard */ +void baseboard_devtree_update(void); +/* Modify devictree settings during ramstage by dedicated variant */ void variant_devtree_update(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index 5955b2a..17d39ae 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -21,8 +21,15 @@ }, }; -void variant_devtree_update(void) +void __weak variant_devtree_update(void) { + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + size_t total_entries = ARRAY_SIZE(limits); variant_update_cpu_power_limits(limits, total_entries); } + +void baseboard_devtree_update(void) +{ + variant_devtree_update(); +} diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index 02bdca5d..7c096510 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -96,8 +96,10 @@ }; #endif -void variant_devtree_update(void) +void __weak variant_devtree_update(void) { + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + const struct cpu_tdp_power_limits *limits = performance_efficient_limits; size_t limits_size = ARRAY_SIZE(performance_efficient_limits); @@ -115,3 +117,8 @@ variant_update_cpu_power_limits(limits, limits_size); } + +void baseboard_devtree_update(void) +{ + variant_devtree_update(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Gerrit-Change-Number: 79329 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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