coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM in Kconfig
by Karthik Ramasubramanian (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Ivy Jian, Nick Vaccaro, Paul Menzel, Shelley Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: mb/google/brox: Fix configuration for TPM in Kconfig ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Ideally this patch can be squashed together with the next CL in the stack. -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 18:44:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Set TPM i2c config in device tree
by Karthik Ramasubramanian (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Eric Lai, Ivy Jian, Nick Vaccaro, Shelley Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79101?usp=email ) Change subject: mb/google/brox: Set TPM i2c config in device tree ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79101/comment/9470c632_0022fb99 : PS4, Line 107: .early_init = 1, Now that GSC is in I2C4, this should be for i2c[4]. https://review.coreboot.org/c/coreboot/+/79101/comment/e89ff4a0_41510cd0 : PS4, Line 169: device ref i2c3 on end Can be removed, not that nothing is in I2C3. -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 18:43:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/genoa: Implement romstage
by Paul Menzel (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Varshit Pandya. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76514?usp=email ) Change subject: soc/amd/genoa: Implement romstage ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2837c4a2b0ec8dcd9dd99602f9c073999c36139 Gerrit-Change-Number: 76514 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Nov 2023 18:40:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: Add USB configuration
by Martin L Roth (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Arthur Heymans, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76517?usp=email ) Change subject: soc/amd/genoa: Add USB configuration ...................................................................... Patch Set 5: (1 comment) File src/vendorcode/amd/opensil/ramstage.c: https://review.coreboot.org/c/coreboot/+/76517/comment/e7657893_4871e791 : PS2, Line 65: struct device *dev = pcidev_on_root(0x18, 0); : assert(dev); : const config_t *soc_config = (config_t *)dev->chip_info; : assert(soc_config); > config_of_soc() can be used with CB:77168 This patch was split into two parts. This one is now about Genoa, so this comment now goes with CB:78919 and has been resolved there. -- To view, visit https://review.coreboot.org/c/coreboot/+/76517?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9 Gerrit-Change-Number: 76517 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Nov 2023 18:28:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Configure Acoustic noise mitigation
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79323?usp=email ) Change subject: mb/google/rex/var/screebo: Configure Acoustic noise mitigation ...................................................................... mb/google/rex/var/screebo: Configure Acoustic noise mitigation Enable Acoustic noise mitigation for google/screebo and set slew rate to 1/8 for IA domain and ignore the slew rate for SA domain. BUG=b:312405633, TEST=Able to build and boot google/screebo. Before: [SPEW ] AcousticNoiseMitigation : 0x0 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x0 [SPEW ] SlowSlewRate for Index = 0 : 0x0 After: [SPEW ] AcousticNoiseMitigation : 0x1 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x1 [SPEW ] SlowSlewRate for Index = 0 : 0x2 Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79323/1 diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 8be0e85..0d9984f 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -90,6 +90,15 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Acoustic Noise settings and slew rate configuration: + # slew rate for IA Domain: Fast/8 + # Ignore slew rate configuration for SA Domain + register "enable_acoustic_noise_mitigation" = "1" + register "disable_fast_pkgc_ramp[VR_DOMAIN_IA]" = "1" + register "slow_slew_rate_config[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate_config[VR_DOMAIN_SA]" = "SLEW_IGNORE" + + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/79323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568 Gerrit-Change-Number: 79323 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDs
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79302?usp=email ) Change subject: soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDs ...................................................................... soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDs This patch allows to override acoustic noise mitigation FSP UPDs: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:312405633 TEST=Able to override the acoustic noise UPDs. Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/fsp_params.c 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79302/1 diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 59b6a8b..cfef3c1 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -129,6 +129,22 @@ NUM_VR_DOMAINS }; +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16, + SLEW_IGNORE = 0xff, +}; + struct soc_intel_meteorlake_config { /* Common struct containing soc config data required by common code */ @@ -499,6 +515,16 @@ /* Platform Power Pmax in Watts. Zero means automatic. */ uint16_t psys_pmax_watts; + + /* Enable or Disable Acoustic Noise Mitigation feature */ + uint8_t enable_acoustic_noise_mitigation; + /* Disable Fast Slew Rate for Deep Package C States for VR domains */ + uint8_t disable_fast_pkgc_ramp[NUM_VR_DOMAINS]; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * as per `enum slew_rate` data type. + */ + uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 9534fc1..2e169b4 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -387,6 +387,20 @@ } } +static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_meteorlake_config *config) +{ + if (!config->enable_acoustic_noise_mitigation) + return; + + m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation; + + for (int i = 0; i < NUM_VR_DOMAINS; i++) { + m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i]; + m_cfg->SlowSlewRate[i] = config->slow_slew_rate_config[i]; + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -410,6 +424,7 @@ fill_fspm_trace_params, fill_fspm_vr_config_params, fill_fspm_ibecc_params, + fill_fsps_acoustic_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/79302?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Gerrit-Change-Number: 79302 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation
by Subrata Banik (Code Review) 28 Nov '23

28 Nov '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79301?usp=email ) Change subject: vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation ...................................................................... vc/intel/fsp/mtl: Add UPDs for Acoustic Noise Mitigation Acoustic noise in PCBs is a common problem and be caused by a variety of factors, including: Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal expansion. This patch adds the UPDs to FSPM header file for mitigating the acoustic noise. FSPM: 1. AcousticNoiseMitigation 2. FastPkgCRampDisable 3. SlowSlewRate BUG=b:312405633 TEST=Able to build and boot google/rex. Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 82 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79301/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 7853004..58923f1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1416,7 +1416,18 @@ /** Offset 0x0585 - Reserved **/ - UINT8 Reserved32[145]; + UINT8 Reserved32[142]; + +/** Offset 0x0613 - Acoustic Noise Mitigation feature + Enabling this option will help mitigate acoustic noise on certain SKUs when the + CPU is in deeper C state. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x0614 - Reserved +**/ + UINT8 Reserved33[2]; /** Offset 0x0616 - Platform Power Pmax PSYS PMax power, defined in 1/8 Watt increments. 0 - Auto Specified in 1/8 @@ -1426,7 +1437,7 @@ /** Offset 0x0618 - Reserved **/ - UINT8 Reserved33[12]; + UINT8 Reserved34[12]; /** Offset 0x0624 - AcLoadline AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 @@ -1465,7 +1476,7 @@ /** Offset 0x0660 - Reserved **/ - UINT8 Reserved34[54]; + UINT8 Reserved35[54]; /** Offset 0x0696 - Thermal Design Current enable/disable Thermal Design Current enable/disable; 0: Disable; 1: Enable. [0] for IA, @@ -1482,7 +1493,29 @@ /** Offset 0x06B4 - Reserved **/ - UINT8 Reserved35[166]; + UINT8 Reserved36[128]; + +/** Offset 0x0734 - Disable Fast Slew Rate for Deep Package C States for VR domains + This option needs to be configured to reduce acoustic noise during deeper C states. + False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp + during deeper C state. [0] for IA, [1] for GT, [2] for SA, [3] through [5] are + Reserved. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[6]; + +/** Offset 0x073A - Slew Rate configuration for Deep Package C States for VR domains + Set VR IA/GT/SA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate + equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew + rate to help minimize acoustic noise; divide by 16 is disabled for GT/SA. 0: + Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16; 0xFF: Ignore the configuration + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16, 0xFF: Ignore the configuration +**/ + UINT8 SlowSlewRate[6]; + +/** Offset 0x0740 - Reserved +**/ + UINT8 Reserved37[26]; /** Offset 0x075A - VR Fast Vmode ICC Limit support Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds @@ -1508,7 +1541,7 @@ /** Offset 0x0772 - Reserved **/ - UINT8 Reserved36[146]; + UINT8 Reserved38[146]; /** Offset 0x0804 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1530,7 +1563,7 @@ /** Offset 0x0807 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved39; /** Offset 0x0808 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1544,7 +1577,7 @@ /** Offset 0x0810 - Reserved **/ - UINT8 Reserved38[8]; + UINT8 Reserved40[8]; /** Offset 0x0818 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable @@ -1599,7 +1632,7 @@ /** Offset 0x0849 - Reserved **/ - UINT8 Reserved39[32]; + UINT8 Reserved41[32]; /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1786,7 +1819,7 @@ /** Offset 0x0A85 - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved42; /** Offset 0x0A86 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1806,7 +1839,7 @@ /** Offset 0x0A99 - Reserved **/ - UINT8 Reserved41[16]; + UINT8 Reserved43[16]; /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1815,7 +1848,7 @@ /** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved42[55]; + UINT8 Reserved44[55]; /** Offset 0x0AF0 - Enable PCH PCIE RP Mask Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, @@ -1867,7 +1900,7 @@ /** Offset 0x0AFE - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved45[2]; /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -1887,7 +1920,7 @@ /** Offset 0x0B11 - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved46[3]; /** Offset 0x0B14 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1912,7 +1945,7 @@ /** Offset 0x0B27 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved47; /** Offset 0x0B28 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T @@ -1928,7 +1961,7 @@ /** Offset 0x0B2A - Reserved **/ - UINT8 Reserved46[6]; + UINT8 Reserved48[6]; /** Offset 0x0B30 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -1938,7 +1971,7 @@ /** Offset 0x0B31 - Reserved **/ - UINT8 Reserved47[11]; + UINT8 Reserved49[11]; /** Offset 0x0B3C - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1960,7 +1993,7 @@ /** Offset 0x0B3F - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved50; /** Offset 0x0B40 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1988,7 +2021,7 @@ /** Offset 0x0B47 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved51; /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2004,7 +2037,7 @@ /** Offset 0x0B4D - Reserved **/ - UINT8 Reserved50; + UINT8 Reserved52; /** Offset 0x0B4E - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -2018,7 +2051,7 @@ /** Offset 0x0B50 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved53; /** Offset 0x0B51 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -2136,7 +2169,7 @@ /** Offset 0x0B64 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved54; /** Offset 0x0B65 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D @@ -2164,7 +2197,7 @@ /** Offset 0x0B69 - Reserved **/ - UINT8 Reserved53[10]; + UINT8 Reserved55[10]; /** Offset 0x0B73 - Read Equalization Training Enables/Disable Read Equalization Training @@ -2174,7 +2207,7 @@ /** Offset 0x0B74 - Reserved **/ - UINT8 Reserved54[2]; + UINT8 Reserved56[2]; /** Offset 0x0B76 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D @@ -2202,7 +2235,7 @@ /** Offset 0x0B7A - Reserved **/ - UINT8 Reserved55; + UINT8 Reserved57; /** Offset 0x0B7B - Command Voltage Centering Enables/Disable Command Voltage Centering @@ -2230,7 +2263,7 @@ /** Offset 0x0B7F - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved58; /** Offset 0x0B80 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test @@ -2282,7 +2315,7 @@ /** Offset 0x0B88 - Reserved **/ - UINT8 Reserved57[2]; + UINT8 Reserved59[2]; /** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2292,7 +2325,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved58[3]; + UINT8 Reserved60[3]; /** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2314,7 +2347,7 @@ /** Offset 0x0B91 - Reserved **/ - UINT8 Reserved59[4]; + UINT8 Reserved61[4]; /** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2324,7 +2357,7 @@ /** Offset 0x0B96 - Reserved **/ - UINT8 Reserved60[17]; + UINT8 Reserved62[17]; /** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2358,7 +2391,7 @@ /** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved63; /** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2450,7 +2483,7 @@ /** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved62[4]; + UINT8 Reserved64[4]; /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2709,7 +2742,7 @@ /** Offset 0x0C2B - Reserved **/ - UINT8 Reserved63[2]; + UINT8 Reserved65[2]; /** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2760,7 +2793,7 @@ /** Offset 0x0C35 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved66; /** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2797,7 +2830,7 @@ /** Offset 0x0C3B - Reserved **/ - UINT8 Reserved65[8]; + UINT8 Reserved67[8]; /** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. @@ -2812,7 +2845,7 @@ /** Offset 0x0C45 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved68; /** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2832,7 +2865,7 @@ /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved67[2]; + UINT8 Reserved69[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2875,7 +2908,7 @@ /** Offset 0x0C62 - Reserved **/ - UINT8 Reserved68[11]; + UINT8 Reserved70[11]; /** Offset 0x0C6D - RH pTRR LFSR1 Mask Row Hammer pTRR LFSR1 Mask, 1/2^(value) @@ -2884,7 +2917,7 @@ /** Offset 0x0C6E - Reserved **/ - UINT8 Reserved69; + UINT8 Reserved71; /** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2900,7 +2933,7 @@ /** Offset 0x0C71 - Reserved **/ - UINT8 Reserved70[3]; + UINT8 Reserved72[3]; /** Offset 0x0C74 - LowerBasicMemTestSize Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable @@ -2910,7 +2943,7 @@ /** Offset 0x0C75 - Reserved **/ - UINT8 Reserved71[20]; + UINT8 Reserved73[20]; /** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2946,7 +2979,7 @@ /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved72[2]; + UINT8 Reserved74[2]; /** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2960,7 +2993,7 @@ /** Offset 0x0C95 - Reserved **/ - UINT8 Reserved73[143]; + UINT8 Reserved75[143]; /** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2976,7 +3009,7 @@ /** Offset 0x0D28 - Reserved **/ - UINT8 Reserved74[28]; + UINT8 Reserved76[28]; /** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2992,7 +3025,7 @@ /** Offset 0x0D46 - Reserved **/ - UINT8 Reserved75[2]; + UINT8 Reserved77[2]; /** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -3003,7 +3036,7 @@ /** Offset 0x0D49 - Reserved **/ - UINT8 Reserved76[34]; + UINT8 Reserved78[34]; /** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -3056,7 +3089,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved77[100]; + UINT8 Reserved79[100]; /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -3079,7 +3112,7 @@ /** Offset 0x0DDA - Reserved **/ - UINT8 Reserved78[2]; + UINT8 Reserved80[2]; /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3105,7 +3138,7 @@ /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved79[164]; + UINT8 Reserved81[164]; /** Offset 0x0E90 - TME Exclude Base Address TME Exclude Base Address. @@ -3125,7 +3158,7 @@ /** Offset 0x0EA1 - Reserved **/ - UINT8 Reserved80[7]; + UINT8 Reserved82[7]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/79301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Gerrit-Change-Number: 79301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: security/tpm/crtm: Add measure additional CBFS files
by Martin L Roth (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Sven Anderson. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77356?usp=email ) Change subject: security/tpm/crtm: Add measure additional CBFS files ...................................................................... Patch Set 8: (1 comment) File src/security/tpm/tspi/crtm.c: https://review.coreboot.org/c/coreboot/+/77356/comment/7ba67e44_ae028c80 : PS8, Line 236: > But @paulepanter@mailbox.org suggested to not use an ifdef at all. […] You don't need to worry about it - just write the function as if CONFIG_TPM_MEASURED_BOOT_ADDITIONAL_FILES were always enabled, because to this function it is. If the config isn't enabled, this function won't be called since the boot state init entry won't be added. The linker will just optimize this function out completely. ``` static void tspi_measure_additional_files(void *unused) { char files[] = CONFIG_TPM_MEASURED_BOOT_ADDITIONAL_FILES; const char *delim = " "; char *file, *pos; printk(BIOS_INFO, "TPM: Measure additional files: %s\n", files); for (file = strtok_r(files, delim, &pos); file; file = strtok_r(NULL, delim, &pos)) { cbfs_unmap(cbfs_map(file, NULL)); } } ``` Let me know if you'd like any help with getting the patch merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/77356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7e1fb3787f496f7ddddf5cdc5f14c02acdc8066 Gerrit-Change-Number: 77356 Gerrit-PatchSet: 8 Gerrit-Owner: Sven Anderson <sven(a)anderson.de> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sven Anderson <sven(a)anderson.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 28 Nov 2023 17:38:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sven Anderson <sven(a)anderson.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Milosevic, Felix Singer, Julius Werner, Lean Sheng Tan, Martin L Roth, Nico Huber, ron minnich. Hello Arthur Heymans, Christian Walter, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74798?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to add a Kconfig option (ARM64_CURRENT_EL) which lets us specify coreboot's EL upon entry. Based on that, we access the appropriate ELx registers. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/Kconfig M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/boot.c M src/arch/arm64/include/arch/asm.h M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 12 files changed, 117 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 12 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 22: (3 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/23a9c341_872ce435 : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > Well, QEMU-SBSA is a rather simple example, with a homogenuous hierarchy and caches known at compile time. I just wonder how it will look like for a more complex setup when one has to allocate struct pptt_cache nodes at runtime. Then it would be harder to reuse the nodes and their pointers. But I guess we can handle that if/when the time comes. Agreed. I think we can close this discussion? File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/080ee310_c67e88ca : PS21, Line 148: cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list); > In https://uefi. […] Considered doing that. Not sure anymore why exactly, but I decided against it. I think the current solution is fine. File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78071/comment/fc4258af_99784003 : PS21, Line 1448: u32 size_valid : 1; : u32 n_sets_valid : 1; : u32 associativity_valid : 1; : u32 alloc_type_valid : 1; : u32 cache_type_valid : 1; : u32 write_policy_valid : 1; : u32 line_size_valid : 1; : u32 cache_id_valid : 1; : u32 reserved : 24; > Bitfields or not, unless the table is defined to be in host […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 22 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 28 Nov 2023 17:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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