coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Krystian Hebel (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Michał Żygowski, Nico Huber, Patrick Rudolph. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/abdbf22e_e00199f9 : PS10, Line 709: pciexp_configure_max_payload > This is what I did: […] Drop testing for !root in `while`, it is handled later inside the loop. ``` while (pdev->bus && pdev->bus->dev) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Nov 2023 14:29:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: Add Protectli to ships-with-coreboot hw list
by Paul Menzel (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Filip Lewiński, Michał Kopeć, Michał Żygowski. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79215?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Documentation: Add Protectli to ships-with-coreboot hw list ...................................................................... Patch Set 1: (3 comments) File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/79215/comment/25a1015b_55924579 : PS1, Line 51: [Dasharo](https://dasharo.com/) Fits on the line above? https://review.coreboot.org/c/coreboot/+/79215/comment/87cce622_365791d0 : PS1, Line 49: proprietary : vendors and expensive contracts. It is supported by : [Dasharo](https://dasharo.com/) coreboot based firmware, maintained by : [3mdeb](https://3mdeb.com/) I haven’t read the other description, but as FSP is probably used in their products, parts of the firmware are also proprietary. “proprietary vendor” is also not well defined, I’d say. https://review.coreboot.org/c/coreboot/+/79215/comment/86abb68b_1919c43a : PS1, Line 53: Linux It’s not a distribution. -- To view, visit https://review.coreboot.org/c/coreboot/+/79215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Gerrit-Change-Number: 79215 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 14:27:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 10: (1 comment) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/9d48df88_7786efb1 : PS10, Line 709: pciexp_configure_max_payload > > dev == dev->bus->dev is how we identify the root device. Don't ask […] This is what I did: ```C static bool pciexp_device_is_root_port(struct device *dev) { u16 flags; u16 cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (!cap) return false; flags = pci_read_config16(dev, cap + PCI_EXP_FLAGS) & PCI_EXP_FLAGS_TYPE; return ((flags >> 4) == PCI_EXP_TYPE_ROOT_PORT); } static void pciexp_configure_max_payload_size(struct device *dev) { unsigned int root_cap, cap; struct device *pdev = dev; /* Walk up the chain and adjust MaxPayload to the minimum supported in the chain */ while (pdev->bus && pdev->bus->dev && !pciexp_device_is_root_port(pdev)) { cap = pci_find_capability(pdev, PCI_CAP_ID_PCIE); root_cap = pci_find_capability(pdev->bus->dev, PCI_CAP_ID_PCIE); printk(BIOS_DEBUG, "Setting Max Paylaod Size for %s device and %s parent\n", dev_path(pdev), dev_path(pdev->bus->dev)); if (!cap || !root_cap) return; if (pdev->bus->dev == pdev || pdev->bus->dev->path.type != DEVICE_PATH_PCI) break; /* Adjust Max_Payload_Size */ pciexp_set_max_payload_size(pdev->bus->dev, root_cap, pdev, cap); pdev = pdev->bus->dev; }; } static void pciexp_tune_dev(struct device *dev) { ... pciexp_configure_max_payload_size(dev); pciexp_configure_ltr(root, root_cap, dev, cap); } ``` What I get in cbmem log as a result: https://paste.dasharo.com/?d1b97978265f7ede#ABLvEctaviQN4acGhVKMgURvSWaxH43… As one can see, the pciexp_set_max_payload_size does not get called for the root port as it should (because pdev->bus->dev never points to a parent bridge/root port). -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 28 Nov 2023 14:23:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: Documentation: Add Protectli to ships-with-coreboot hw list
by Krystian Hebel (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Filip Lewiński, Michał Kopeć, Michał Żygowski. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79215?usp=email ) Change subject: Documentation: Add Protectli to ships-with-coreboot hw list ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Gerrit-Change-Number: 79215 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Filip Lewiński Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 14:11:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 28 Nov '23

28 Nov '23

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[S] Change in coreboot[main]: acpi/acpi_gic: Add GIC ITS subtable
by Nico Huber (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Lean Sheng Tan, Maximilian Brune, Naresh Solanki, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78115?usp=email ) Change subject: acpi/acpi_gic: Add GIC ITS subtable ...................................................................... Patch Set 5: (1 comment) File src/acpi/acpi_gic.c: https://review.coreboot.org/c/coreboot/+/78115/comment/68c81f92_248933e5 : PS5, Line 92: &its_base It needs a `uintptr_t *` pointing to an array. But that could only work if you'd know the size in advance... It seems the code is not even build tested. I suggest to postpone this review until there is a platform that uses ACPI_COMMON_MADT_GICC_V3. -- To view, visit https://review.coreboot.org/c/coreboot/+/78115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Gerrit-Change-Number: 78115 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 13:23:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/genoa: Add openSIL to Genoa Kconfig
by Felix Held (Code Review) 28 Nov '23

28 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78635?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/genoa: Add openSIL to Genoa Kconfig ...................................................................... soc/amd/genoa: Add openSIL to Genoa Kconfig Select opensil & opensil_genoa. This enables openSIL for Genoa, allowing the build to be tested. Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78635 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Varshit Pandya: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 973677d5..a98e634 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -36,6 +36,8 @@ select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_OPENSIL + select SOC_AMD_OPENSIL_GENOA select X86_CUSTOM_BOOTMEDIA config USE_EXP_X86_64_SUPPORT -- To view, visit https://review.coreboot.org/c/coreboot/+/78635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18379f311a56ff3f8b68d3c9a07a4f59de2d90b2 Gerrit-Change-Number: 78635 Gerrit-PatchSet: 12 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vendorcode/amd: Hook up opensil
by Felix Held (Code Review) 28 Nov '23

28 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76511?usp=email ) Change subject: vendorcode/amd: Hook up opensil ...................................................................... vendorcode/amd: Hook up opensil OpenSIL has a native buildsystem using meson and configuration mechanism using kconfiglib. To be able to use the coreboot toolchain with opensil, meson crossfiles are used, which get generated by coreboot makefiles. Configuration of opensil is done in a similar fashion with a template defconfig after which kconfiglib is called to generate headers. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ide2d181914116119dfd37b1511d89ea965729141 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/vendorcode/amd/Kconfig M src/vendorcode/amd/Makefile.inc A src/vendorcode/amd/opensil/Kconfig A src/vendorcode/amd/opensil/Kconfig.debug A src/vendorcode/amd/opensil/Makefile.inc A src/vendorcode/amd/opensil/genoa_poc/meson_cross.template A src/vendorcode/amd/opensil/genoa_poc/opensil_config.template 7 files changed, 228 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index b095916..c667ae2 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -17,3 +17,10 @@ endmenu endif + +config SOC_AMD_OPENSIL + bool + help + Select this on SoCs that use opensil. + +source "src/vendorcode/amd/opensil/Kconfig" diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc index 3210134..bc66a8d 100644 --- a/src/vendorcode/amd/Makefile.inc +++ b/src/vendorcode/amd/Makefile.inc @@ -1,2 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + subdirs-$(CONFIG_SOC_AMD_STONEYRIDGE) += pi subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += pi +subdirs-$(CONFIG_SOC_AMD_OPENSIL) += opensil diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig new file mode 100644 index 0000000..29c22b6 --- /dev/null +++ b/src/vendorcode/amd/opensil/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if SOC_AMD_OPENSIL + +config SOC_AMD_OPENSIL_GENOA + bool + help + Select this on SoCs that use the Genoa version of opensil. + +config AMD_OPENSIL_PATH + string + default "$(top)/src/vendorcode/amd/opensil/genoa_poc/opensil" if SOC_AMD_OPENSIL_GENOA + help + Set to the path of the openSIL directory containing meson.build. + example + +endif diff --git a/src/vendorcode/amd/opensil/Kconfig.debug b/src/vendorcode/amd/opensil/Kconfig.debug new file mode 100644 index 0000000..d49b37d --- /dev/null +++ b/src/vendorcode/amd/opensil/Kconfig.debug @@ -0,0 +1,71 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if SOC_AMD_OPENSIL + +config OPENSIL_DEBUG_OUTPUT + bool "OpenSIL console output" + default y + help + Select this if you want OpenSIL debug messages compiled + in the image. + +if OPENSIL_DEBUG_OUTPUT + +config OPENSIL_DEBUG_PREFIX + bool "Print the opensil prefix" + default n + help + This prints the function name and line level in front of the + actual message. + +config OPENSIL_DEBUG_APOB + bool "Enable APOB messages" + default n + help + Enable printing APOB related messages. + +config OPENSIL_DEBUG_NBIO + bool "Enable NBIO messages" + default y + help + Enable printing NBIO related messages. + +config OPENSIL_DEBUG_CCX + bool "Enable CCX messages" + default y + help + Enable printing CCX related messages. + +config OPENSIL_DEBUG_SMU + bool "Enable SMU messages" + default y + help + Enable printing SMU related messages. + +config OPENSIL_DEBUG_DF + bool "Enable DF messages" + default y + help + Enable printing DF related messages. + +config OPENSIL_DEBUG_MEM + bool "Enable MEM messages" + default y + help + Enable printing MEM related messages. + +config OPENSIL_DEBUG_FCH + bool "Enable FCH messages" + default y + help + Enable printing FCH related messages. + +config OPENSIL_DEBUG_RAS + bool "Enable RAS messages" + default y + help + Enable printing RAS related messages. + +endif # OPENSIL_DEBUG_OUTPUT + +endif # SOC_AMD_OPENSIL diff --git a/src/vendorcode/amd/opensil/Makefile.inc b/src/vendorcode/amd/opensil/Makefile.inc new file mode 100644 index 0000000..5afe075 --- /dev/null +++ b/src/vendorcode/amd/opensil/Makefile.inc @@ -0,0 +1,91 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_AMD_OPENSIL),y) + +ifneq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) + $(error OpenSIL can only be built for either x86 or x86_64) +endif + +opensil_dir := $(call strip_quotes,$(CONFIG_AMD_OPENSIL_PATH)) + +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +cpu_family_string="x86" +cpu_string="i686" +opensil_target_name=AMDopensil32 +is_32bit="true" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +clang_args=\'-m32\'\, \'-fno-pic\'\, +endif +endif + +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_64),y) +cpu_family_string="x86_64" +cpu_string="x86_64" +opensil_target_name=AMDopensil64 +is_32bit="false" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +clang_args=\'-fno-pic\'\, +endif +endif + +ifeq ($(CONFIG_OPENSIL_DEBUG_OUTPUT),y) +sil_debug_enable="true" +else +sil_debug_enable="false" +endif + +# check if $(obj) is an absolute or a relative path +ifeq ($(shell printf %.1s "$(obj)"),/) +OBJPATH = $(obj) +else +OBJPATH = $(top)/$(obj) +endif + +PYTHON?=python + +OPENSIL_CONFIG=opensil_config + +bios_base=$(shell printf "%x" $(call int-subtract, $(CONFIG_ROMSTAGE_ADDR) $(CONFIG_C_ENV_BOOTBLOCK_SIZE))) +bios_size=$(CONFIG_C_ENV_BOOTBLOCK_SIZE) + +$(OBJPATH)/$(OPENSIL_CONFIG): $(opensil_dir)/../opensil_config.template + sed -e "s,##APOB_BASE##,$(CONFIG_PSP_APOB_DRAM_ADDRESS)," \ + -e "s,##BIOS_ENTRY_BASE##,$(bios_base)," \ + -e "s,##BIOS_ENTRY_SIZE##,$(bios_size) ," \ + $< > $@ + +$(OBJPATH)/$(OPENSIL_CONFIG).h: $(OBJPATH)/$(OPENSIL_CONFIG) $(obj)/config.h $(objutil)/kconfig/conf + cd $(opensil_dir); KCONFIG_CONFIG=$(OBJPATH)/$(OPENSIL_CONFIG) KCONFIG_AUTOHEADER=$@ $(PYTHON) util/kconfig/lib/genconfig.py Kconfig + +# meson handles ccache on its own +OPENSIL_COMPILER=$(filter-out $(CCACHE), $(CC_ramstage)) + +$(OBJPATH)/meson_crosscompile: $(opensil_dir)/../meson_cross.template $(obj)/config.h $(OBJPATH)/$(OPENSIL_CONFIG).h + sed -e "s,##COMPILER##,$(OPENSIL_COMPILER)," \ + -e "s,##AR##,$(AR_ramstage)," \ + -e "s,##NASM##,$(NASM)," \ + -e "s,##COREBOOT_DIR##,$(top)," \ + -e "s,##OPENSIL_DIR##,$(opensil_dir)," \ + -e "s,##OBJPATH##,$(OBJPATH)," \ + -e "s,##CPU_FAMILY##,$(cpu_family_string)," \ + -e "s,##CPU##,$(cpu_string)," \ + -e "s,##IS32BIT##,$(is_32bit)," \ + -e "s,##SIL_DEBUG_ENABLE##,$(sil_debug_enable)," \ + -e "s,##CLANG_ARGS##,$(clang_args)," \ + $< > $@ + +# Don't set a meson buildtype as opensil is broken when compiler optimizations are enabled +$(OBJPATH)/opensil: $(OBJPATH)/meson_crosscompile $(obj)/config.h + cd $(opensil_dir); meson setup --cross-file $< $(OBJPATH)/opensil -Db_staticpic=false \ + -DPlatKcfgDir=$(OBJPATH) -DPlatKcfg=$(OPENSIL_CONFIG) + +$(OBJPATH)/opensil/lib$(opensil_target_name).a: $(OBJPATH)/opensil + meson compile -C $(OBJPATH)/opensil $(opensil_target_name) + +$(OBJPATH)/opensil.a: $(OBJPATH)/opensil/lib$(opensil_target_name).a + cp $(OBJPATH)/opensil/lib$(opensil_target_name).a $@ + +romstage-libs += $(OBJPATH)/opensil.a +ramstage-libs += $(OBJPATH)/opensil.a + +endif diff --git a/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template b/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template new file mode 100644 index 0000000..b457c80 --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/meson_cross.template @@ -0,0 +1,34 @@ +[binaries] +c = '##COMPILER##' +ar = '##AR##' +nasm = '##NASM##' + +[built-in options] +c_args = ['-nostdinc', + '-I##OBJPATH##', + '-I##COREBOOT_DIR##/src/include', + '-I##COREBOOT_DIR##/src/arch/x86/include', + '-I##COREBOOT_DIR##/src/commonlib/include', + '-I##COREBOOT_DIR##/src/commonlib/bsd/include', + '-include', '##COREBOOT_DIR##/src/include/kconfig.h', + '-include', '##OBJPATH##/config.h', + '-include', '##COREBOOT_DIR##/src/commonlib/bsd/include/commonlib/bsd/compiler.h', + '-DHAS_STRING_H=1', + # openSIL isn't compatible with coreboot's assert implementation, so use special case + '-D_PORTING_H_=1', + '-DSIL_DEBUG_ENABLE=##SIL_DEBUG_ENABLE##', + # openSIL uses coreboot assert which uses printk which warns about unused-param + '-Wno-unused-parameter', + # ubiquitous problem in openSIL + '-Wno-missing-field-initializers', + ##CLANG_ARGS## + ] + +[host_machine] +system = 'linux' +cpu_family = '##CPU_FAMILY##' +cpu = '##CPU##' +endian = 'little' + +[properties] +is32bit = ##IS32BIT## diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil_config.template b/src/vendorcode/amd/opensil/genoa_poc/opensil_config.template new file mode 100644 index 0000000..2ddd3b4 --- /dev/null +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil_config.template @@ -0,0 +1,5 @@ +CONFIG_PLAT_APOB_ADDRESS=##APOB_BASE## +CONFIG_PSP_BIOS_BIN_BASE=##BIOS_ENTRY_BASE## +CONFIG_PSP_BIOS_BIN_SIZE=##BIOS_ENTRY_SIZE## +CONFIG_PLAT_NUMBER_SOCKETS=1 +CONFIG_SOC_F19M10=y -- To view, visit https://review.coreboot.org/c/coreboot/+/76511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide2d181914116119dfd37b1511d89ea965729141 Gerrit-Change-Number: 76511 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Change GPP_B14 from NC to NF
by Kun Liu (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun. Kun Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79308?usp=email ) Change subject: mb/google/rex/var/screebo: Change GPP_B14 from NC to NF ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79308/comment/d5df23d3_4884b38c : PS1, Line 12: =emerge-rex coreboot > please highlight the problem and the resolution with this CL. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79308?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Gerrit-Change-Number: 79308 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Nov 2023 13:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/screebo: Change GPP_B14 from NC to NF
by Kun Liu (Code Review) 28 Nov '23

28 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Kun Liu, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Rui Zhou, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79308?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/screebo: Change GPP_B14 from NC to NF ...................................................................... mb/google/rex/var/screebo: Change GPP_B14 from NC to NF Change GPP_B14 from NC to NF BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/79308/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79308?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Gerrit-Change-Number: 79308 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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