Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79218?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
......................................................................
arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
We seem to be passing CPPFLAGS to linker in x86 arch
ramstage. This is superflous as these are only meant
to be compiler flags and should not be passed to the
linker.
Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878
Signed-off-by: Srinivas Hegde <srinivashegde(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79218
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
---
M src/arch/x86/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Jérémy Compostella: Looks good to me, but someone else must approve
Julius Werner: Looks good to me, approved
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 75b9d3d..62294a6 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -317,7 +317,7 @@
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
@printf " CC $(subst $(obj)/,,$(@))\n"
- $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
+ $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
@printf " CC $(subst $(obj)/,,$(@))\n"
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Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79292?usp=email )
Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1
......................................................................
Patch Set 4:
(1 comment)
This change is ready for review.
Patchset:
PS1:
> you can take a look into CL: https://review.coreboot. […]
I rebased this CL on the previous gpio.c CL.
Since KConfig, and devicetree are set for the baseboard ovis,
The only difference I see is that for Ovis we have:
PAD_CFG_GPI_SCI_LOW(GPP_D18, NONE, DEEP, EDGE_SINGLE),
While for Deku I have
PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, INVERT),
So if I understand you correctly, it should only be routed to SCI.
I corrected that.
(Ovis is missing the other LAN, so it would need to be corrected in another CL for Ovis)
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Change subject: soc/mediatek/mt8188: Support loading OP-TEE via an SMC
......................................................................
Patch Set 16:
(1 comment)
File src/soc/mediatek/mt8188/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/78801/comment/4a2227ed_a2fa2d01 :
PS15, Line 62: BL31_MAKEARGS
> Done
Please update the codebase and rebase the patch after CB:79333 is merged.
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Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79333?usp=email )
Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Update arm-trusted-firmware submodule to upstream master
Updating from commit id 88b2d8134:
2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration)
to commit id e7486343d:
2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration)
This brings in 451 new commits.
Change-Id: I75a89c6f0d60ccccd8ff42954416666dabef717f
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/79333/1
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 88b2d81..e748634 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 88b2d81345dfd84902aae586a743d00ac5df2f48
+Subproject commit e7486343d46a0d60047233adfd8a64436bbac1fd
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Change subject: soc/amd/genoa: Implement romstage
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/soc/amd/genoa/romstage.c:
https://review.coreboot.org/c/coreboot/+/76514/comment/a1dd7136_ef73fbeb :
PS6, Line 3: #include <cbmem.h>
might be good to sort the include
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Change subject: vendorcode/amd/opensil: Implement cbmem_top_chipset
......................................................................
Patch Set 6:
(1 comment)
File src/vendorcode/amd/opensil/genoa_poc/romstage.c:
https://review.coreboot.org/c/coreboot/+/76513/comment/f037bda9_5701b551 :
PS6, Line 16: top_mem
i'd replace this with top_mem - CONFIG_SMM_TSEG_SIZE and drop line 14. the should result in the same behavior, but be a bit easier to follow
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Change subject: arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79218/comment/e5b60f58_cb7e46f8 :
PS4, Line 10: ramstage. This is superflous as these are only meant to be compiler flags and should not be passed to the linker.
> Please wrap at 72 characters max.
Done
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Hello Julius Werner, Jérémy Compostella, Patrick Georgi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79218?usp=email
to look at the new patch set (#5).
Change subject: arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
......................................................................
arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker
We seem to be passing CPPFLAGS to linker in x86 arch
ramstage. This is superflous as these are only meant
to be compiler flags and should not be passed to the
linker.
Change-Id: Ia3cd51be6be252aa796191cf0d2cd91d393c8878
Signed-off-by: Srinivas Hegde <srinivashegde(a)google.com>
---
M src/arch/x86/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/79218/5
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