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Change subject: mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.
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Patch Set 7: Code-Review+1
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Change subject: Update arm-trusted-firmware submodule to upstream master
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Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Tune eMMC DLL values
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Patch Set 8: Code-Review+2
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79334?usp=email )
Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
......................................................................
mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.
On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.
This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.
Test=Boot into Linux and make sure a write access into the EEPROM is
possible.
Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/79334/1
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index 28fca2d..d386d75 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -38,4 +38,8 @@
/* Enable Row-Hammer prevention */
memupd->FspmConfig.RhPrevention = 1;
+ if (CONFIG(BOARD_SIEMENS_MC_EHL1)) {
+ /* Allow writes to EEPROM addresses 0x50..0x57. */
+ memupd->FspmConfig.SmbusSpdWriteDisable = 0;
+ }
}
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Change subject: vc/intel/fsp/mtl: Export pre-memory graphics FSP-M UPDs
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
I assume this CL is no more required if we are uprev to FSP 3424.88
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Change subject: mb/google/nissa/var/anraggar: Tune eMMC DLL values
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Patch Set 8: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Tune eMMC DLL values
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78851/comment/078a0994_adba7029 :
PS6, Line 7: Update eMMC DLL tuning values
> Tune eMMC DLL values
Done
https://review.coreboot.org/c/coreboot/+/78851/comment/b877fb1b_8f3a52d7 :
PS6, Line 9: Update eMMC DLL tuning values for improved initialization reliability
> Please start by describing the problem.
Done
https://review.coreboot.org/c/coreboot/+/78851/comment/4d823c54_796d1017 :
PS6, Line 9: Update eMMC DLL tuning values for improved initialization reliability
> How did you determine the values?
Done
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