coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
by Daniel Peng (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Daniel Peng, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79335?usp=email to look at the new patch set (#3). Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values ...................................................................... mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/79335/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Gerrit-Change-Number: 79335 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
by Daniel Peng (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Daniel Peng, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79335?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values ...................................................................... mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values As customer demand, it is necessary to add a 60 sec running score "PL1=17W" table to the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/79335/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Gerrit-Change-Number: 79335 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: Fix configuration for TPM
by Shelley Chen (Code Review) 29 Nov '23

29 Nov '23

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: mb/google/brox: Fix configuration for TPM ...................................................................... mb/google/brox: Fix configuration for TPM On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. Also, fixing up the TPM entry in the device tree. Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 2 files changed, 16 insertions(+), 18 deletions(-) Approvals: Ivy Jian: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 08a0656..f6f33b6 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -76,7 +76,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x1 if BOARD_GOOGLE_BROX + default 0x4 if BOARD_GOOGLE_BROX config DRIVER_TPM_I2C_ADDR hex @@ -87,7 +87,7 @@ config TPM_TIS_ACPI_INTERRUPT int - default 13 + default 66 # GPE0_DW2_02 (GPP_E2) config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 2b73ad2..c8b4c5a 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -76,14 +76,12 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio and WFC | - #| I2C1 | cr50 TPM. Early init is | + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | ISH Sensor | + #| I2C4 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | - #| I2C2 | SAR0 | - #| I2C3 | Touchscreen | - #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { @@ -94,24 +92,18 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, + .rise_time_ns = 600, .fall_time_ns = 400, .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 900, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, .rise_time_ns = 600, .fall_time_ns = 400, .data_hold_time_ns = 50, }, - .i2c[5] = { + .i2c[4] = { + .early_init = 1, .speed = I2C_SPEED_FAST, .rise_time_ns = 650, .fall_time_ns = 400, @@ -167,7 +159,13 @@ device generic 0 on end end end - device ref i2c3 on end + device ref i2c4 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E2_IRQ)" + device i2c 50 on end + end + end device ref heci1 on end device ref sata on end device ref pcie_rp8 on -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
by Eric Lai (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Daniel Peng, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79335?usp=email ) Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79335/comment/9d447f27_e72e87dd : PS1, Line 9: it is necessary to add a 60 sec running : score I don't know what is this. Maybe describe what the different of performance by add the change? -- To view, visit https://review.coreboot.org/c/coreboot/+/79335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Gerrit-Change-Number: 79335 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 29 Nov 2023 06:54:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
by Daniel Peng (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79335?usp=email ) Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Gerrit-Change-Number: 79335 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Nov 2023 06:54:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
by Mario Scheithauer (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79334?usp=email ) Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79334?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Gerrit-Change-Number: 79334 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 29 Nov 2023 06:53:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values
by Daniel Peng (Code Review) 29 Nov '23

29 Nov '23

Daniel Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79335?usp=email ) Change subject: mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values ...................................................................... mb/google/brya/var/marasov: Update MSR Package Power Limit-1 values As customer demand, it is necessary to add a 60 sec running score "PL1=17W" table to the DTT setting to optimize performance. BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/79335/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index a8c1c06..6c1f3f9 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -134,6 +134,12 @@ register "tcc_offset" = "5" # TCC of 100 + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 17, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + device domain 0 on device ref igpu on chip drivers/gfx/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/79335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Gerrit-Change-Number: 79335 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Fix Type-C & DP functions
by Weimin Wu (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Nick Vaccaro, Paul Menzel, Subrata Banik. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79165?usp=email ) Change subject: mb/google/nissa/var/anraggar: Fix Type-C & DP functions ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79165/comment/5c771e78_7ad6c90d : PS5, Line 10: relate > relative? or related? not sure. sorry, it's related. it's mean USB2P_1, USB2N_1 and USB2P_2, USB2N_2 are not exchanged, but TCP0 and TCP1 are exchanged. -- To view, visit https://review.coreboot.org/c/coreboot/+/79165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Gerrit-Change-Number: 79165 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Nov 2023 06:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Fix Type-C & DP functions
by Weimin Wu (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Nick Vaccaro, Paul Menzel, Subrata Banik, Weimin Wu. Hello Dolan Liu, Eric Lai, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79165?usp=email to look at the new patch set (#6). Change subject: mb/google/nissa/var/anraggar: Fix Type-C & DP functions ...................................................................... mb/google/nissa/var/anraggar: Fix Type-C & DP functions Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/79165/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Gerrit-Change-Number: 79165 Gerrit-PatchSet: 6 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: util/docker/archlinux: Add more packages allowing CI builds
by Felix Singer (Code Review) 29 Nov '23

29 Nov '23

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79314?usp=email ) Change subject: util/docker/archlinux: Add more packages allowing CI builds ...................................................................... Patch Set 4: (3 comments) File util/docker/archlinux/Dockerfile: https://review.coreboot.org/c/coreboot/+/79314/comment/aa65c656_ae917506 : PS3, Line 15: bash-completion \ > Add bc Done https://review.coreboot.org/c/coreboot/+/79314/comment/6894dd13_85b3d884 : PS3, Line 19: cscope \ > Add dtc Done https://review.coreboot.org/c/coreboot/+/79314/comment/ac30df93_1dd3caaf : PS3, Line 25: less \ > Add meson. Required for opensil. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I757e6dbac557bcb640777b819529a978bf54ed93 Gerrit-Change-Number: 79314 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 29 Nov 2023 06:31:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2023