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Change subject: mb/google/nissa/var/quandiso: Add LTE only daughterboard support
......................................................................
Patch Set 5: Code-Review+1
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Change subject: mb/google/rex/var/deku: Enable LAN0, LAN1
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79292/comment/b02be71e_058e378e :
PS4, Line 9: Add overridetree.cb entry to configure the LAN0 LAN1 devices.
Maybe add an introductory sentence. google/deku is a Chromebox featuring two LAN ports.
File src/mainboard/google/rex/variants/deku/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79292/comment/c1d44c3a_6965d44e :
PS4, Line 72: #PCIE7 LAN1 card
Please add a space after the #.
https://review.coreboot.org/c/coreboot/+/79292/comment/4f6e02e9_50b5920e :
PS4, Line 87: #PCIE10 LAN0 card
Please add a space after the #.
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Change subject: mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera device
......................................................................
Patch Set 3: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79163/comment/22ab243e_420aaacd :
PS3, Line 11: Sensor:OV13B10-GA5A
: Driver:DW9714V
: EEPROM:GT24P64E
Please add a space after the colon.
https://review.coreboot.org/c/coreboot/+/79163/comment/da538b89_39873d40 :
PS3, Line 15:
Please also mention the source. Like schematics?
https://review.coreboot.org/c/coreboot/+/79163/comment/0239376d_4e685818 :
PS3, Line 17: TEST=Google Camera app working
Please paste the related log messages from coreboot and the Linux kernel.
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Hello Karthik Ramasubramanian, Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79295?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+1 by Shelley Chen, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Update storage settings for SSD and UFS
......................................................................
mb/google/brox: Update storage settings for SSD and UFS
Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configured related gpio
settings.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpect overrides.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
M src/mainboard/google/brox/variants/brox/gpio.c
4 files changed, 38 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/79295/3
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Change subject: mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79334/comment/f50d8c1a_ac0f7340 :
PS1, Line 12: On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
I’d add a blank line between paragraphs.
https://review.coreboot.org/c/coreboot/+/79334/comment/79ade01b_390bbfb9 :
PS1, Line 19: Test=Boot into Linux and make sure a write access into the EEPROM is
: possible.
Maybe list the command you used to do that.
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