coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[S] Change in coreboot[main]: soc/amd/common: use common physical address bit reservation code
by Felix Held (Code Review) 02 Oct '23

02 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email ) Change subject: soc/amd/common: use common physical address bit reservation code ...................................................................... soc/amd/common: use common physical address bit reservation code Instead of having the get_usable_physical_address_bits function that only got used in the data fabric domain resource reporting code, drop this function, select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT in the common AMD non-CAR CPU and rename get_sme_reserved_address_bits to get_reserved_phys_addr_bits so that the common cpu_phys_address_size function will return the correct number of usable physical address bits which now can be used everywhere. The common AMD CAR CPU support is only selected by Stoneyridge which doesn't support secure memory encryption, so RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT isn't selected by the SOC_AMD_COMMON_BLOCK_CAR Kconfig option. Before only the MMIO region reporting took the reserved physical address bits into account, but now also the MTRR calculation will take those reserved bits into account. See the AMD64 Programmers Manual volume 2 (document number 24593) for details. Chapter 7.10.5 from revision 3.41 of this document was used as a reference. The MTRR handling code in older Linux kernels complains when the upper reserved bits in the MTRR mask weren't set, but sets them after complaining and then continues to boot. This issue is no longer present in version 6.5 of the Linux kernel. The calculation of the TSEG mask however still needs to take all physical bits into account, including the ones reserved for the memory encryption. When not setting the reserved bits in the TSEG mask, the Mandolin board with a Picasso APU won't boot to the OS any more due to not returning from SeaBIOS calling into the VBIOS. Haven't root-caused what exactly causes this breakage, but I think previously when something else was wrong with the SMM initialization, also something went wrong when calling into the VBIOS. TEST=Ubuntu 2023.10 nightly build boots on Mandolin via SeaBIOS and EDK2 and Windows 10 boots on it via EDK2. TEST=On Ubuntu 2022.04 LTS, the kernel complained with the following warning, but it still continues the boot process as described above: mtrr: your BIOS has configured an incorrect mask, fixing it. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/Makefile.inc M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/cpu.h 6 files changed, 12 insertions(+), 10 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 6c5329a..f926887 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -13,6 +13,7 @@ config SOC_AMD_COMMON_BLOCK_NONCAR bool + select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT help From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any more, since the RAM initialization is already done by the PSP when diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index 3204667..f8ca357 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) bootblock-y += bootblock.c +bootblock-y += cpu.c bootblock-y += early_cache.c bootblock-y += pre_c.S bootblock-y += write_resume_eip.c diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index eec593c..eefd62f 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -35,7 +35,8 @@ wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } -static uint32_t get_sme_reserved_address_bits(void) +/* Number of most significant physical address bits reserved for secure memory encryption */ +unsigned int get_reserved_phys_addr_bits(void) { if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE) return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & @@ -44,8 +45,3 @@ else return 0; } - -uint32_t get_usable_physical_address_bits(void) -{ - return cpu_phys_address_size() - get_sme_reserved_address_bits(); -} diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index 4004726..ae00885 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -65,6 +65,11 @@ uintptr_t tseg_base; size_t tseg_size; + /* For the TSEG masks all physical address bits including the ones reserved for memory + encryption need to be taken into account. TODO: Find out why this is the case */ + const unsigned int total_physical_address_bits = + cpu_phys_address_size() + get_reserved_phys_addr_bits(); + smm_region(&tseg_base, &tseg_size); msr_t msr; @@ -73,7 +78,7 @@ msr.lo = ~(tseg_size - 1); msr.lo |= SMM_TSEG_WB; - msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + msr.hi = (1 << (total_physical_address_bits - 32)) - 1; wrmsr(SMM_MASK_MSR, msr); uintptr_t smbase = smm_get_cpu_smbase(cpu_index()); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index ca685b2..01fad99 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <amdblocks/cpu.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> #include <arch/vga.h> #include <console/console.h> #include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> #include <device/device.h> #include <device/pci_ops.h> #include <types.h> @@ -90,7 +90,7 @@ /* The last 12GB of the usable address space are reserved and can't be used for MMIO */ const resource_t reserved_upper_mmio_base = - (1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE; + (1ULL << cpu_phys_address_size()) - DF_RESERVED_TOP_12GB_MMIO_SIZE; for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i)); diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 10dd23f..4aa225b 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -12,7 +12,6 @@ int get_cpu_count(void); unsigned int get_threads_per_core(void); void set_cstate_io_addr(void); -uint32_t get_usable_physical_address_bits(void); void write_resume_eip(void); union pstate_msr; /* proper definition is in soc/msr.h */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Gerrit-Change-Number: 78074 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Felix Held (Code Review) 02 Oct '23

02 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... x86/include/arch/cpuid.h: Fix inline assembly In the cpuid helper functions eax is always written to by the cpuid instruction, so add it to the output clobbered list. This prevents GCC from generating code with undefined behaviour when the function is inlined. Test: Verified that the generated assembly is sane and runtime tests showed no "strange" behaviour when calling cpuid functions. Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78192 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/arch/x86/include/arch/cpuid.h 1 file changed, 9 insertions(+), 12 deletions(-) Approvals: Felix Held: Looks good to me, but someone else must approve Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/arch/x86/include/arch/cpuid.h b/src/arch/x86/include/arch/cpuid.h index 70a5beb..b2780be 100644 --- a/src/arch/x86/include/arch/cpuid.h +++ b/src/arch/x86/include/arch/cpuid.h @@ -56,39 +56,36 @@ return eax; } -static inline uint32_t cpuid_ebx(const uint32_t eax) +static inline uint32_t cpuid_ebx(uint32_t eax) { uint32_t ebx; asm volatile( "cpuid;" - : "=b" (ebx) - : "a" (eax) - : "ecx", "edx"); + : "=b" (ebx), "+a" (eax) + :: "ecx", "edx"); return ebx; } -static inline uint32_t cpuid_ecx(const uint32_t eax) +static inline uint32_t cpuid_ecx(uint32_t eax) { uint32_t ecx; asm volatile( "cpuid;" - : "=c" (ecx) - : "a" (eax) - : "ebx", "edx"); + : "=c" (ecx), "+a" (eax) + :: "ebx", "edx"); return ecx; } -static inline uint32_t cpuid_edx(const uint32_t eax) +static inline uint32_t cpuid_edx(uint32_t eax) { uint32_t edx; asm volatile( "cpuid;" - : "=d" (edx) - : "a" (eax) - : "ebx", "ecx"); + : "=d" (edx), "+a" (eax) + :: "ebx", "ecx"); return edx; } -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID
by Yidi Lin (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78209?usp=email ) Change subject: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78209/comment/3a96de20_662e6a80 : PS1, Line 9: The tolerance of ADC voltage table is too small > … causing …. Done https://review.coreboot.org/c/coreboot/+/78209/comment/9e0644a1_1fbe4436 : PS1, Line 10: accordring > according Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Gerrit-Change-Number: 78209 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 13:31:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID
by Yidi Lin (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78209?usp=email to look at the new patch set (#2). Change subject: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID ...................................................................... mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID The voltage values are adjusted according to the suggestion from the hardware team to ensure that ADC voltage has enough tolerance. This is the follow-up patch of CB:78063. There is no actual issue. BRANCH=none BUG=b:301908091 TEST=check firmware screen Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/geralt/boardid.c 1 file changed, 15 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78209/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Gerrit-Change-Number: 78209 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: mb: Enable VBOOT_LID_SWITCH by default for ChromeOS
by Subrata Banik (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Alexander Couzens, Christian Walter, Eran Mitrani, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Martin Roth, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Paul Menzel, Piotr Król, Sean Rhodes, Stefan Ott, Tarun, Werner Zeh, Yidi Lin, Yu-Ping Wu. Hello Alexander Couzens, Christian Walter, Eran Mitrani, Erik van den Bogaert, Felix Held, Frans Hendriks, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jason Nien, Julius Werner, Kapil Porwal, Martin Roth, Michael Niewöhner, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Stefan Ott, Tarun, Werner Zeh, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78207?usp=email to look at the new patch set (#7). Change subject: mb: Enable VBOOT_LID_SWITCH by default for ChromeOS ...................................................................... mb: Enable VBOOT_LID_SWITCH by default for ChromeOS Remove mainboard-specific overrides to VBOOT_LID_SWITCH config. VBOOT_LID_SWITCH is now enabled by default for all ChromeOS devices (except the Chromebox and Chromebase). Platforms that wish to disable VBOOT_LID_SWITCH should override the config from mainboard Kconfig. TEST=Ensure VBOOT_LID_SWITCH is enabled for google/rex, but not applicable for Ovis (aka Chromebox). Change-Id: I922c04e0fa0675090cea7c7b3f4e2275eb70f523 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cherry/Kconfig M src/mainboard/google/corsola/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/foster/Kconfig M src/mainboard/google/gale/Kconfig M src/mainboard/google/geralt/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kukui/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/mistral/Kconfig M src/mainboard/google/myst/Kconfig M src/mainboard/google/nyan/Kconfig M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_blaze/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/puff/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/rex/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/smaug/Kconfig M src/mainboard/google/storm/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/zork/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/security/vboot/Kconfig 56 files changed, 81 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/78207/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I922c04e0fa0675090cea7c7b3f4e2275eb70f523 Gerrit-Change-Number: 78207 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, cong yang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78185?usp=email ) Change subject: mb/google/starmie: Add 3 ms delay to AW37503 Power IC panel timing ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I488c746d1fcfc165125b0ecccb0bccbb99231b00 Gerrit-Change-Number: 78185 Gerrit-PatchSet: 6 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 11:17:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78209?usp=email ) Change subject: mb/google/geralt: Update voltage mapping tables for RAM ID and LCMD ID ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78209/comment/211b7a4d_b507f96c : PS1, Line 9: The tolerance of ADC voltage table is too small … causing …. https://review.coreboot.org/c/coreboot/+/78209/comment/92e34f03_5ff04ea6 : PS1, Line 10: accordring according -- To view, visit https://review.coreboot.org/c/coreboot/+/78209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c Gerrit-Change-Number: 78209 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 11:16:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/geralt: Remove SAMSUNG_ATANA33XC20 panel support
by Paul Menzel (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78210?usp=email ) Change subject: mb/google/geralt: Remove SAMSUNG_ATANA33XC20 panel support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97ed5b341724ed42098b2c17d0eb75eab881dbb1 Gerrit-Change-Number: 78210 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 11:16:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: Update fsp submodule to upstream master branch
by Felix Singer (Code Review) 02 Oct '23

02 Oct '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78189?usp=email ) Change subject: Update fsp submodule to upstream master branch ...................................................................... Update fsp submodule to upstream master branch Updating from commit id a72794810884 (2023-09-07): IoT ADL-N MR1 (4172_00) to commit id 481ea7cf0bae (2023-09-19): Move to RaptorLakeFspBinPkg.dec This brings in 9 new commits: 481ea7cf0b Move to RaptorLakeFspBinPkg.dec 55e25b819e Raptor Lake FSP C.1.BD.40 2b0aac4f64 Raptor Lake FSP C.0.BD.40 3fa75657aa Add Client Raptor Lake FSP 8d24189361 Add Alder Lake and Raptor Lake to README.md 98f4a1fe2f Rename to AlderlakeSiliconPkg c78a6784cb Add FvLateSilicon for Alder Lake 849ce8261b Tiger Lake FSP A.0.7E.70 4b0b1eb4e3 Update SplitFspBin.py to latest from edk2 Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78189 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved Felix Singer: Looks good to me, approved Michał Żygowski: Looks good to me, approved diff --git a/3rdparty/fsp b/3rdparty/fsp index a727948..481ea7c 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit a72794810884966001c927a5f202a46eb5161488 +Subproject commit 481ea7cf0bae0107c3e14aa746e52657647142f3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94 Gerrit-Change-Number: 78189 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: Update fsp submodule to upstream master branch
by Felix Singer (Code Review) 02 Oct '23

02 Oct '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78189?usp=email ) Change subject: Update fsp submodule to upstream master branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94 Gerrit-Change-Number: 78189 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 02 Oct 2023 11:02:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023